High-rate rll encoding

ABSTRACT

An unencoded m-bit data input sequence is divided into a block of n bits and a block of m-n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D 2 ) precoding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m−n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.

RELATED APPLICATION DATA

The present application is a continuation application of, and claims thepriority benefit of, commonly-assigned and co-pending U.S. applicationSer. No. 11/749,711, entitled HIGH-RATE RLL ENCODING, filed on May 16,2007, which application is hereby incorporated herein by reference inits entirety.

TECHNICAL FIELD

The present invention relates generally to RLL encoding and, inparticular, to designing a mother code having a first rate which maythen be used to design additional, higher-rate codes.

BACKGROUND ART

Runlength-limited (RLL) codes have been widely used in magnetic andoptical data storage to eliminate sequences that are undesired for theprocesses of recording and reproducing digital data. Various classes ofRLL codes are used in practice. For example, peak detection systemsemploying runlength-limited RLL(d,k) constrained codes such as rate-½μLL(2,7) and rate-⅔ μLL(1,7) codes have been predominant in digitalmagnetic storage at low normalized linear densities. At moderatenormalized linear densities, the introduction of partial-responsemaximum-likelihood (PRML) detection channels into data storage requireda different type of constrained codes. This class of codes, which areknown as PRML(G,I) or PRML(0,G,I) codes, facilitates timing recovery andgain control, and limits the path memory length of the sequencedetector, and therefore the decoding delay, without significantlydegrading detector performance. PRML(G,I) codes may also be used inconjunction with 1/(1⊕D²) precoders and with noise-predictive,maximum-likelihood (NPML) channels which generalize the PRML concept (⊕stands for the logical exclusive-OR operation). The G constraint limitsthe maximum runlength of zeros at the modulation encoder output (inputof 1/(1⊕D²) precoder) to G. The I constraint limits the maximumrunlength of zeros in the even and odd interleave of the encoder output(input of 1/(1⊕D²) precoder) to I.

The first PRML(G, I) code that was implemented in a data storage devicehad the code rate 8/9 and satisfied the constraints G=4 and I=4. Inaddition, it satisfied a VFO constraint, which is also known as the Mconstraint, allowing discrimination of encoded data from thesynchronization preamble and therefore fast start-up of the PRMLreceiver. The M constraint limits the maximum runlength of ones at themodulation encoder output (input of 1/(1⊕D²) precoder) to M. The classof RLL codes satisfying G, I and M constraints is known as PRML(G, I, M)codes. The recorded VFO pattern . . . ++−−++−− . . . (the output of a1/(1⊕D²) precoder) is received as a tone with frequency 1/(4T) at thecenter of the channel. The VFO constraint (M constraint) was generalizedto constraints used to construct anti-whistle codes that exclude datapatterns with zero or one spectral component in the frequency band (0,1/(2T)). Hard disk drive (HDD) products often used architectures thatdid not require the VFO constraint. Therefore, high-rate PRML codes withrates higher than 8/9, which have been designed, satisfy G and Iconstraints but not necessarily the M constraint.

The RLL code used in Linear Tape Open (LTO) standards for generations 2to 4 (hereinafter LTO 2-4) is a twins-constrained maximum-transition-runMTR(j,k,t) code that requires 1/(1⊕D) precoding. It satisfies j, k and tconstraints at the input of the 1/(1⊕D) precoder. The k constraintlimits the maximum runlength of zeros at the modulation encoder output(input of 1/(1⊕D) precoder) to k. The j constraint limits the maximumrunlength of ones at the modulation encoder output (input of 1(1⊕D)precoder) to j. The twins constraint t limits the maximum number ofconsecutive twins (pair of zeros or pair of ones) at the modulationencoder output (input of 1/(1⊕D) precoder) to t. The G and I constraintsat the input of 1/(1⊕D²) precoders are equivalent to constraints j=G+1,k=G+1 and t=1 at the input of 1/(1⊕D) precoders where both set ofconstraints PRML(G,I) and MTR(j,k,t) give rise to the same set ofconstraints on recorded patterns (output of precoder). The RLL code inLTO 2-4 is based on a rate-8/9 code that also satisfies the VFOconstraint, rules out the Data Set Separator (DSS) and Resynchronization(Re Sync) patterns and ensures that each RLL codeword has at least oneisolated transition. The concatenated rate of the RLL code in LTO 2-4 is16/17 because a rate-8/9 encoded byte is concatenated with an uncodedbyte. The constraints satisfied by the rate-16/17 RLL code in LTO 2-4are equivalent to G=13, I=11 and M=23. Additionally, the RLL codeparameter that is very important to error-rate performance witherror-correction-coding (ECC) is error propagation. Error propagation isdefined as the minimum length of a channel error burst in NRZ bits thatcauses two erroneous symbols in one Reed-Solomon (RS) codeword at the RSdecoder input. Error propagation depends on the modulation codeproperties and the depth of interleaving of ECC codewords. In LTO 2-4two-way interleaved RS codewords are RLL encoded and the errorpropagation of the modulation code is therefore 9 NRZ bits. Since mostof the error patterns at the detector output are 1 to 4 NRZ bits long,most of the time one symbol in a RS codeword is in error as a result ofa short (non-fading) error burst in the channel.

Construction of rate-8/9 PRML(G, I, M) codes has previously beendescribed. Additionally, the rate of non-concatenated PRML(G, I, M)codes that have been constructed is less than 16/17.

The next generation LTO standard (LTO 5) will likely have a rate-32/33or rate-48/49 RLL code in order to increase the format efficiency. Onemethod for the design of such codes is the straightforward extension ofthe rate-16/17 LTO 2-4 code by inserting two or four more uncoded bytesto obtain a rate-32/33 or rate-48/49 code, respectively. However, thissolution results in a rate-32/33 RLL code with parameters G=29, I=19,M=39 or a rate-48/49 RLL code with parameters G=45, I=27, M=55. Thesevalues are not acceptable because the constraints are too weak. Anothersolution would be to generate a rate-16/17 encode and decode table usinga computer and use computer-aided design tools to generate Boolean-basedor ROM-based logic for encoding and decoding based on the encode anddecode table. However, this solution is too complex and would requiremore than 500,000 gates per channel to implement. Additionally, theencoding operation needs a compact representation such that it can beincluded into the LTO 5 standard; specifying 65,536 17-bit codewords inthe LTO 5 standard is not acceptable. Therefore, there is a need for analgorithmic approach to design an RLL code that satisfies similarconstraints as the LTO 2-4 RLL code does.

SUMMARY OF THE INVENTION

The present invention provides a method for encoding a data inputsequence of m bits into an output sequence codeword of m+1 bits, where mis an integer multiple of an ECC symbol size s. The method includes thesteps of receiving a data stream of unencoded m-bit input sequences anddividing each m-bit input sequence into a first block of n bits and asecond block of m−n unencoded bits, where n is an integer multiple of s.The first block of n bits is divided into a first set of n+1 encodedbits, wherein at least one of P1 subblocks of the first set of n+1 bitssatisfies a G constraint, an M constraint and an/constraint. The firstset of n+1 encoded bits is mapped in a one-to-one manner into a secondset of n+1 encoded bits wherein at least one of P2 subblocks of thesecond set of n+1 bits gives rise to at least Q1 transitions after1/(1+D²) precoding. The second set of n+1 encoded bits is divided intoP3 encoded subblocks and the P3 encoded subblocks are interleaved among(m−n)/s unencoded symbols so as to form the (m+1)-bit output sequencecodeword. The output sequence codeword is then stored on a data storagemedium.

In one embodiment, an encoder generates a rate-16/17 PRML(G=6, I=7,M=15) mother code from which higher rate codes may be generated. Invarious embodiments, such higher rate codes include a rate-32/33PRML(G=14, I=11, M=23) code (RLL 1), a rate-48/49 PRML(G=22, I=15, M=31)code (RLL 2) and a rate-48/49 PRML(G=14, I=19, M=39) code (RLL 3).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a high level block diagram of a data storage device in whichthe present invention may be implemented;

FIG. 2A is a block diagram of a rate-16/17 encoder to generate themother code of the present invention;

FIG. 2B is a block diagram of a decoder of the present invention;

FIGS. 3A, 3B and 3C are representations of the output blocks from thefirst, second and third stages, respectively, of the rate-16/17 encoderof the present invention;

FIG. 4 illustrates the process by which an input of four 8-bit symbolsis transformed into a rate-33-bit codeword for a 32/33 code bymultiplexing coded and uncoded bits;

FIGS. 5A, 5B illustrate a 4-way interleaving (multiplexing) scheme of8-bit symbols at the output of four C1 Reed-Solomon encoders which maybe implemented for the rate-32/33 PRML(G=14, I=11, M=23) code of thepresent invention;

FIG. 6 illustrates a 4-way C1 interleaving scheme which may beimplemented for the rate-48/49 PRML(G=22, I=15, M=31) code of thepresent invention; and

FIG. 7 illustrates a 4-way C1 interleaving scheme which may beimplemented for the rate-48/49 PRML(G=14, I=19, M=39) code of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Many of the functional units described in this specification have beenillustrated in the Figures as blocks, in order to more particularlyemphasize their implementation independence. For example, a block may beimplemented as a hardware circuit comprising custom VLSI circuits orgate arrays, off-the-shelf semiconductors such as logic chips,transistors, or other discrete components. A block may also beimplemented in programmable hardware devices such as field programmablegate arrays, programmable array logic, programmable logic devices or thelike.

Blocks may also be implemented in software for execution by varioustypes of processors. An identified block of executable code may, forinstance, comprise one or more physical or logical blocks of computerinstructions which may, for instance, be organized as an object,procedure, or function. Nevertheless, the executables of an identifiedblock need not be physically located together, but may comprisedisparate instructions stored in different locations which, when joinedlogically together, comprise the block and achieve the stated purposefor the block.

Indeed, a block of executable code could be a single instruction, ormany instructions, and may even be distributed over several differentcode segments, among different programs, and across several memorydevices. Similarly, operational data may be identified and illustratedherein within blocks, and may be embodied in any suitable form andorganized within any suitable type of data structure. The operationaldata may be collected as a single data set, or may be distributed overdifferent locations including over different storage devices, and mayexist, at least partially, merely as electronic signals on a system ornetwork.

Furthermore, the described features, structures, or characteristics ofthe invention may be combined in any suitable manner in one or moreembodiments. In the following description, numerous specific details areprovided, such as examples of programming, software blocks, logicblocks, user selections, network transactions, database queries,database structures, hardware blocks, hardware circuits, hardware chips,etc., to provide a thorough understanding of embodiments of theinvention. One skilled in the relevant art will recognize, however, thatthe invention may be practiced without one or more of the specificdetails, or with other methods, components, and so forth. In otherinstances, well-known steps, components or operations are not shown ordescribed in detail to avoid obscuring aspects of the invention.

The present invention provides an algorithmic approach to the design ofhigher-rate PRML(G, I, M) codes which also enforce a minimum number oftransitions per codeword. A rate-16/17 PRML(G=6, I=7, M=15) “mothercode” is provided that enforces at least four transitions per codeword.To this end the input to the encoder is partitioned into a first set ofblocks which are mapped into a second set of blocks and G, I and Mconstraints are imposed on at least one of the second set of blocks. Theencoding operation is initially performed by detecting violations andindicating in encoded data the type of violations that have occurred.Further stages of encoding by violation detection and substitutiontighten the code constraints and rule out DSS and Re Sync patterns. Themother code is then used to construct higher-rate 32/33 or 48/49 PRML(G,I, M) codes by combining uncoded 8-bit bytes with the 17-bit output fromthe mother code. The present invention also provides a rate-32/33PRML(G=14, I=11, M=23) code (RLL 1), a rate-48/49 PRML(G=22, I=15, M=31)code (RLL 2) and a rate-48/49 PRML(G=14, I=19, M=39) code (RLL 3).

Notation

The notations x(i) and x_(i) are used interchangeably herein to denotethe components of a vector x. The following representations are used fora row vector x with n components

x=[x(1)x(2) . . . x(n)]=[x ₁ x ₂ . . . x _(n) ]=[x1x2 . . . xn]=x(1:n)

Column vectors are often specified by the transpose of a row vector andthe superscript T is used to indicate the transpose operation.

Two different notations are used herein for Boolean operations. Thefollowing convention has been used to specify Boolean code constraintsand to perform Boolean operations involving multiplication of a matrixand a vector: overbar stands for negation, multiplication for AND, andaddition for OR. Among these three operations, negation has the highestprecedence, AND (multiplication) has second highest precedence and OR(addition) has the lowest precedence. Exclusive-OR (XOR) is indicated by⊕.

Encoder and decoder hardware based on Boolean logic is specified usingthe MATLAB notation for Boolean operations. In particular, ˜ stands fornegation, & for AND, and | for OR. Again, among these three operations,negation (˜) has the highest precedence, followed by AND (&) and OR (|)which has the lowest precedence, i.e., the usual Boolean precedencerules apply.

The next section describes the requirements upon the resulting codes interms of prohibited output sequences, which therefore determines therequirements on the mother code. The steps in creating the mother codeare described both in text and via illustration in compact matrixnotation. The section is followed by a section describing acorresponding decoder for the mother code. Next are sections whichinclude Boolean listings in MATLAB format of the requirements for thethird encoding and decoding stages for the mother code. Finally, thelast three sections describe the design of rate-32/33 PRML(G=14, I=11,M=23) code, rate-48/49 PRML(G=22, I=15, M=31) code and rate-48/49PRML(G=14, I=19, M=39) code from the mother code.

FIG. 1 is a high level block diagram of a data storage device 100 inwhich the present invention may be implemented. The device 100 includesan encoder 200 which receives user data from a host 10. The encoder 200encodes the data, as will be described herein, and passes the encodeddata to a precoder 102 which may include write-equalizationfunctionality as in LTO standards. A controller 104 receives theprecoded data and transmits it to a write channel 106 which records theencoded data onto a data storage medium 20.

The storage device 100 further includes a read channel 108 which readsthe data from the storage medium 20 and transmits it to the controller104. The controller 104 sends the data to a detector 110 which processes(e.g., inverse precoding) and passes it on to a decoder 210. The decoderdecodes the data, as will described herein, and sends the decoded datato the host 10.

Construction of Rate-16/17 PRML(G=6, I=7, M=15) Mother Code with MinimumTransition Density

FIG. 2A is a block diagram of the encoder 200. The encoder 200 receivesunencoded user data a(1:16) and, using K encoding stages, outputs arate-16/17 PRML(G=6, I=7, M=15) mother code y(1:17). The example of theencoder 200 which is illustrated and described herein includes K=3encoding stages 202, 204, 206, although more or fewer stages may beused. The output of the k-th encoding stage o_(k) ^(E) (binary columnvector) can be described by the multiplication of a binarytransformation matrix M_(k) ^(E)=g_(k) ^(E)(i_(k) ^(E)) and a binarypartitioning vector n_(k) ^(E)=h_(k) ^(E)(i_(k) ^(E)) (binary columnvector) that depend on the binary input i_(k) ^(E) (binary columnvector) as follows:

o _(k) ^(E) =M _(k) ^(E) n _(k) ^(E) =g _(k) ^(E)(i _(k) ^(E))h _(k)^(E)(i _(k) ^(E))

where the superscript E refers to the encoding operation and theaddition and the multiplication operations in the matrix multiplicationare Boolean OR and Boolean AND operations, respectively. For a given16-bit encoder input, only one of the components of a partitioningvector is one whereas all the other components are zero. This propertyis related to the fact that the input space is partitioned in a mutuallyexclusive manner. Finally, concatenation of encoding stages is done suchthat the output of the k-th encoding stage, for k=1,2 in a three-stagesystem, is the input of the next encoding stage, i.e., i_(k+1)^(E)=o_(k) ^(E).

First Encoder Stage

The first encoder stage 202 ensures that at least one of P₁=4 subblocksof the 17-bit output of the first encoder stage 202 satisfy G, I and Mconstraints. The output o₁ ^(E)=b^(T)=[b₁b₂ . . . b₁₇]^(T) of the firstencoder stage 202 is a 17×1 binary column vector. The P₁=4 subblocks ofthe 17-bit output of the stage 202 are illustrated in FIG. 3A as b₁ b₂b₃ b₄, b₅ b₆ b₇ b₈, b₉ b₁₀ b₁₁ b₁₂ b₁₃ and b₁₄ b₁₅ b₁₆ b₁₇.Concatenation of the four output vectors results in a PRML(G=6, I=9,M=20) code. The first four bits b₁ b₂ b₃ b₄ are not allowed to be allzero. Similarly, the next four bits b₅b₆b₇b₈ are also not allowed to beall zero. The next five bits b₉ b₁₀ b₁₁ b₁₂ b₁₃ are not allowed to beany of the following twelve 5-bit combinations {00000, 00010, 01000,01010, 00001, 00100, 00101, 10000, 10001, 10100, 10101, 11111}, therebyimposing G, I and M constraints on this 5-bit combination. The last fourbits are also not allowed to be all zero. Note that only a G constraintwas imposed on the 4-bit combinations.

The output b may be partitioned into two blocks of size 8 bits and 9bits which will be used to construct a rate-32/33 PRML(G, I, M) code.Similarly, the output b may be partitioned into four blocks of size 4bits, 4 bits, 5 bits and 4 bits which will be used to construct arate-48/49 PRML(G, I, M) code. At the end of the first encoder stage 202there are at most (2⁴−1) (2⁴−1) (2⁵−12) (2⁴−1)=67,500 codewords. Since67,500>2¹⁶ the first stage may be accomplished with a rate-16/17 codemapping 16 bits into 17 bits. Note that only three of the twelveexcluded bit patterns b₉ b₁₀ b₁₁ b₁₂ b₁₃, viz., {00010, 01010, 11111}have a 1 in the fourth position, i.e., b₁₂=1. Therefore, if a₁ a₂a₃ a₄is nonzero, a₅ a₆ a₇ a₈ is nonzero, a₉ a₁₀ a₁₁ a₁₂ is none of the threebit patterns {0000, 0100, 1111} and a₁₃ a₁₄ a₁₅ a₁₆ is nonzero, then the16×1 encoder input vector i₁ ^(E)=a^(T)=[a₁ a₂ . . . a₁₆]^(T) is mappedinto o₁ ^(E)=b^(T)=[b₁ b₂ . . . b₁₇]^(T) using the substitutions [b₁ b₂b₃ b₄]=[a₁ a₂ a₃ a₄], [b₅ b₆ b₇ b₈]=[a₅ a₆ a₇ a₈], [b₉b₁₀ b₁₁ b₁₃]=[a₉a₁₀ a₁₁ a₁₂] [b₁₄ b₁₅ b₁₆ b₁₇]=[a₁₃ a₁₄ a₁₅ a₁₆] and b₁₂=1. Therefore,there are six types of violation that can occur: a₁ a₂ a₃ a₄ is allzero, a₅ a₆ a₇ a₈ is all zero, a₉ a₁₀ a₁₁ a₁₂ is one of the three bitpatterns {0000, 0100, 1111} or a₁₃ a₁₄ a₁₅ a₁₆ is all zero. A violationcan be indicated by b₁₂=0 and b₁₀=1. The type of a single violation canbe indicated by three bits [b₉ b₁₀ b₁₃]. These three bits are notallowed to be all zeros in order not to violate the I code constraint.And one of the three-bit combinations, the all-one bit pattern [b₉ b₁₁b₁₃]=[111] in the example, is used to indicate that more than oneviolation has occurred. Thus, there are exactly six remaining three bitpatterns {001, 010, 011, 100, 101, 110} which can be used to indicatethe type of a single violation. If only one of the patterns a₁ a₂ a₃ a₄,a₅a₆a₇a₈ and a₁₃ a₁₄ a₁₅ a₁₆ is all zero, then the information in a₉ a₁₀a₁₁ a₁₂ is placed into the bit pattern that is in violation. Forexample, if a₅ a₆ a₇ a₈ is all zero, then [b₅ b₆ b₇ b₈]=[a₉ a₁₀ a₁₁a₁₂], etc. One partition for no violations and 6 partitions for a singleviolation have so far been obtained. There are also 12 possible twoviolations and 13 possible three or four violations for a total of1+6+12+13=32 first-stage partitions. If two, three or four violationsoccur, the type of violation is indicated in the output as in the caseof a single violation and the non-violation blocks are reshuffled ifnecessary. In the next section, the exact expression for the 32×1 binarypartitioning vector n₁ ^(E)=h₁ ^(E)(i₁ ^(E))=p^(T)=[p(1) p(2) . . .p(32)]^(T) and binary 17×32 matrix M₁ ^(E)=g₁ ^(E)(i₁ ^(E))=[M_(1,1)^(E)M_(1,2) ^(E)] will be described in terms of two 17×16 submatrices B₁and B₂.

The constraints satisfied by o₁ ^(E)=b′=[b₁ b₂ . . . b₁₇]′ O₁^(E)=b^(T)=[b₁ b₂ . . . b₁₇]^(T) following the first encoder stage 202are

G Constraints:

b ₁ +b ₂ +b ₃ +b ₄=1

b ₅ +b ₆ +b ₇ +b ₈=1

b ₉ +b ₁₀ +b ₁₁ +b ₁₂=1

b ₁₀ +b ₁₁ +b ₁₂ +b ₁₃=1

b ₁₄ +b ₁₅ +b ₁₆ +b ₁₇=1

I Constraints:

b ₉ +b ₁₁ +b ₁₃=1

b ₁₀ +b ₁₂=1

M Constraints:

b₉b₁₀b₁₁b₁₂b₁₃=0

Therefore, the code obtained at the output of the first encoder stage202 is a PRML(G=6, I=9, M=20) code.

Second Encoder Stage

The second encoder stage 204 further tightens the code constraints/and Mby detection of prohibited patterns and subsequent substitution with adesired pattern that does not violate the code can be uniquelyrecognized during the decoding. The first encoder stage 202 ensures thatthe third of the P₁=4 subblocks of the 17-bit output b of the firstencoder stage 202 satisfies G, I and M constraints. The first encoderstage 202 further ensures that the remaining three 4-bit subblockssatisfy a G constraint by not allowing the 4-bit allzero pattern tooccur as a subblock. The second encoder stage 204 remaps undesired17-bit outputs b of the first encoder stage 202 into desired 17-bitoutputs c. FIG. 3B illustrates the two subblocks of the 17-bit output cof the second encoder stage 204. Specifically, the second encoder stage204 detects prohibited patterns and replaces them with substitutepatterns and therefore ensures that the first of the two subblocks ofthe 17-bit output of the second encoder stage 204 c satisfies/and Mconstraints. The first subblock of the 17-bit output of the secondencoder stage 204 is c₁ c₂ c₃ c₄ c₅ C₆ c₇c₈ and the second subblock isc₉ c₁₀ c₁₁ c₁₂ c₁₃ c₁₄ c₁₅ c₁₆ c₁₇. Note that the second subblockalready satisfies I and M constraints as a result of the encoding in thefirst stage. TABLE I shows the prohibited patterns and the correspondingsubstitute patterns in the second encoder stage 204.

TABLE I 17-bit Prohibited Pattern b 17-bit Substitute Pattern c 0 b₂ 0b₄ 0 b₆ 0 b₈ b₉ b₁₀ b₁₁ b₁₂ b₂ 0 b₄ b₁₄ b₆ b₁₀ b₈ b₁₂ b₉ 0 b₁₁ b₁₃ b₁₄b₁₅ b₁₆ b₁₇ 0 b₁₃ 1 b₁₅ b₁₆ b₁₇ b₁ 0 b₃ 0 b₅ 0 b₇ 0 b₉ b₁₀ b₁₁ b₁₄ 1 b₉b₁₅ b₁₁ b₁₀ b₁₃ b₁₂ b₁ 0 b₁₂ b₁₃ b₁₄ b₁₅ b₁₆ b₁₇ b₃ 0 b₅ 1 b₇ b₁₆ b₁₇ 11 1 1 1 1 1 1 b₉ b₁₀ b₁₁ b₁₂ b₁₄ b₁₅ 1 b₉ b₁₀ b₁₁ b₁₂ b₁₃ b₁₃ b₁₄ b₁₅b₁₆ b₁₇ 1 1 1 1 1 0 1 b₁₆ b₁₇

The bold pattern within the prohibited pattern b is used to detectviolations during the second stage of encoding whereas the bold patternin the substitute pattern c or d (if the presence of channel errors anderrors in the first decoder stage 212 is considered, then c, the outputof the second encoder stage 204, becomes d, the input of the seconddecoder stage 214) is used to detect required inverse substitutionduring the second stage of decoding. If none of the three prohibitedpatterns is detected during the second encoder stage 204, the output ofthe second encoder stage 204 is equal to its input, i.e., c=b.Therefore, there are four partitions (three substitutions plus absenceof substitution) in the second encoder stage 204.

The constraints satisfied by o₂ ^(E=c) ^(T)=[c₁ c₂ . . . c₁₇]^(T)following the second encoder stage 204 are

G Constraints:

c ₁ +c ₂ +c ₃ +c ₄=1

c ₅ +c ₆ +c ₇ +c ₈=1

c ₆ +c ₇ +c ₈ +c ₉ +c ₁₀ +c ₁₁ +c ₁₂=1

c ₁₀ +c ₁₁ +c ₁₂ +c ₁₃ +c ₁₄=1

c ₁₄ +c ₁₅ +c ₁₆ +c ₁₇=1

I Constraints:

c ₁ +c ₃ +c ₅ +c ₇=1

c ₂ +c ₄ +c ₆ +c ₈=1

c ₉ +c ₁₁ +c ₁₃=1

c ₁₀ +c ₁₂ +c ₁₄=1

c ₆ +c ₈ +c ₁₀ +c ₁₂=1

M Constraints:

c₉c₁₀c₁₁c₁₂c₁₃c₁₄=0

c ₁ c ₂ c ₃ c ₄ c ₅ c ₆ +c ₇ +c ₈=0

Therefore, the code obtained at the output of the second encoder stage204 is a PRML(G=6, I=7, M=15) code.

Third Encoder Stage

FIG. 3C illustrates the P₂=2 subblocks of the 17-bit output y of thethird encoder stage 206. The third encoder stage 206 increases theminimum transition density and ensures that the output of the encoder ygives rise to at least Q₂=4 transitions in the recorded patternsubsequent to 1/(1⊕D²) precoding. The motivation behind this step is torule out (that is, prevent them from appearing) twolow-transition-density patterns from modulation encoded data: the dataseparator sequence (DSS), a sequence with a period of 24 bits, and the34-bit Re Sync pattern in LTO 4. It is noted that DSS consists ofconsecutive 12T magnets where T is the channel bit period (magnetizationremains the same for an interval of 12T if write equalization is nottaken into account) whereas Re Sync in LTO 4 consists of a 10T magnet,followed by a 11T magnet and a 12T magnet. More specifically, the thirdencoder stage 206 ensures that each of the encoded blocks [y₁ y₂ y₃ y₄y₅ y₆ y₇ y₈] and [y₉ y₁₀ y₁₁ y₁₂ y₁₃ y₁₄ y₁₅ y₁₆ y₁₇] when convertedinto NRZI notation, will result in at least two transitions (NRZI ones).Therefore, the output y of the entire encoder gives rise to at leastQ₂=4 transitions in the recorded pattern subsequent to 1/(1⊕D²)precoding. As previously stated, this code property is used to ensurethat the low-transition-density patterns DSS and Re Sync are ruled outin modulation encoded data.

Coded data y must be precoded using a 1/(1⊕D²) precoder. It is wellknown that a 1(1⊕D²) precoder can be represented by the serialconcatenation of two precoders of type 1/(1⊕D). In LTO 1-4 1/(1⊕D)precoding is performed in conjunction with write equalization.Therefore, 1/(1⊕D) precoding of coded data y would be sufficient. In thefollowing, the notation y′ is used for 1/(1⊕D) precoded coded data y.Note that the components of y′ are bits in NRZI notation (0 representsno transition, 1 represents transition). Uncoded data may either be notprecoded at all, 1/(1⊕D) precoded or 1/(1⊕D²) precoded. From anerror-rate performance viewpoint, it is preferable to not precode theuncoded data. However, because 1/(1⊕D) precoding is already used inconjunction with write equalization in LTO 1-4, it may be more desirableto use the 1/(1⊕D) precoding. Therefore, assuming that 1/(1 ⊕D) (NRZI)precoding is used for uncoded data and the uncoded bit preceding thefirst coded subblock [y₁ y₂ y₃ y₄ y₅ y₆ y₇ y₈] is U₁ and the uncoded bit(NRZI) preceding the second coded subblock [y₉ y₁₀ y₁₁ y₁₂ y₁₃ y₁₄ y₁₅y₁₆ y₁₇] is U₂, the minimum transition density constraints translateinto two sets of requirements.

The first set of requirements, which ensure that the first codedsubblock gives rise to at least Q₁=2 transitions after 1/(1⊕D²)precoding, is

${U_{1} + {\sum\limits_{i = 1}^{8}y_{i}^{\prime}}} \geq 2$

where all of the additions in the above equations are integer additions

y′₁=U₁⊕y₁

y′ _(i) =y′ _(i−1) ⊕y _(i), i=2, . . . , 8

and [y′₁ y′₂ y′₃ y′₄ y′₅ y′₆ y′₇ y′₈] is the 1/(1⊕D) precoded firstsubblock.

The second set of requirements, which ensure that the second codedsubblock gives rise to at least Q₁=2 transitions after 1/(1⊕D²)precoding, is:

${U_{2} + {\sum\limits_{i = 9}^{17}y_{i}^{\prime}}} \geq 2$

where all of the additions in the above equations are integer additions

y′₉=U₂⊕y₉

y′ _(i) =y′ _(i−1) ⊕y _(i), i=10, . . . , 17

and [y′₉ y′₁₀ y′₁₁ y′₁₂ y′₁₃ y′₁₄ y′₁₅ y′₁₆ y′₁₇ ] is the 1/(1⊕D)precoded second subblock.

The third encoder stage 206 remaps undesired 17-bit outputs of thesecond encoder stage 204 c into desired 17-bit outputs y. Specifically,the third encoder stage 206 detects prohibited patterns and replacesthem with substitute patterns to ensure that each of the P₂=2 subblocks(FIG. 3C) of the 17-bit output y of the third encoder stage 206 givesrise to at least two transitions in the recorded pattern subsequent to1/(1⊕D²) precoding. The first subblock of the 17-bit output of the thirdencoder stage 206 is y₁ y₂ y₃ y₄ y₅ y₆ y₇ y₈ and the second subblock isy₉ y₁₀ y₁₁ y₁₂ y₁₃ y₁₄ y₁₅ y₁₆ y₁₇. TABLE II shows the prohibitedpatterns and the corresponding substitute patterns in the third (last)encoding stage.

TABLE II 17-bit Prohibited Pattern c 17-bit Substitute Pattern y 0 0 0 11 0 0 0 c₉ c₁₀ c₁₁ c₁₂ c₁₀ c₁₂ 1 1 0 0 0 0 c₉ 1 c₁₁ 0 c₁₃ c₁₄ c₁₅ c₁₆c₁₇ c₁₃ c₁₄ c₁₅ c₁₆ c₁₇ c₁ c₂ c₃ c₄ c₅ c₆ c₇ c₈ 0 0 0 c₁ c₂ c₃ c₄ c₅ c₆1 1 0 c₇ 0 c₈ 0 1 1 0 0 0 0 1 1 0 1

The bold pattern within the prohibited pattern c is used to detectviolations during the third stage of encoding whereas the bold patternin the substitute pattern y or z (if the presence of channel errors isconsidered, then y, the output of the third encoder stage 206, becomesz, the input of the first decoder stage 212) is used to detect requiredinverse substitution during the first stage of decoding. If none of thetwo prohibited patterns is detected during the third encoder stage 206,the output of the third encoder stage 206 is equal to its input, i.e.,y=c. Therefore, there are three partitions (two substitutions plusabsence of substitution) in the third encoder stage 206.

The constraints satisfied by o₃ ^(E)=y′=[y₁ y₂ . . . y₁₇]′ o₁^(E)=b^(T)=[b₁ b₂ . . . b₁₇]^(T) following the third encoder stage 206are

G Constraints:

y ₁ +y ₂ +y ₃ +y ₄=1

y ₄ +y ₅ +y ₆ +y ₇ +y ₈=1

y ₅ +y ₆ +y ₇ +y ₈ +y ₉ +y ₁₀=1

y ₆ +y ₇ +y ₈ +y ₉ +y ₁₀ +y ₁₁ +y ₁₂=1

y ₁₀ +y ₁₁ +y ₁₂ +y ₁₃ +y ₁₄=1

y ₁₄ +y ₁₅ +y ₁₆ +y ₁₇=1

I Constraints:

y ₁ +y ₃ +y ₅ +y ₇=1

y ₂ +y ₄ +y ₆ +y ₈=1

y ₆ +y ₈ +y ₁₀ +y ₁₂=1

y ₇ +y ₉ +y ₁₁ +y ₁₃=1

y ₉ +y ₁₁ +y ₁₃ +y ₁₅=1

y ₁₀ +y ₁₂ +y ₁₄=1

M Constraints:

y₁y₂y₃y₄y₅y₆y₇y₈=0

y₉y₁₀y₁₁y₁₂y₁₃y₁₄=0

Minimum Transition Density Constraints:

y ₁ +y ₂ +y ₃ + y ₄ + y ₅ +y ₆ +y ₇ +y ₈=1

y ₉ +y ₁₀ +y ₁₁ +y ₁₂ + y ₁₃ + y ₁₄ +y ₁₅ +y ₁₆ +y ₁₇=1

The code obtained at the output of the third (and last, when k=1, 2, 3)encoding stage is a PRML(G=6, I=7, M=15) code that enforces at leastQ₂=4 transitions per codeword. The second and third encoder stages 204,206 may optionally be combined into a single remapping stage ofundesired patterns into desired patterns where remapping occurs in amanner allowing the inverse operation during decoding.

Decoding

FIG. 2B is a block diagram of the decoder 210. The decoder 210 receivesrate-16/17 PRML(G=6, I=7, M=15) encoded data z(1:17) and, using kencoding stages, outputs unencoded user data f(1:16). The example of thedecoder 210 which is illustrated and described herein includes K=3decoding stages 212, 214, 216, although more or fewer stages may beused. The three stages 212, 214, 216, provide the inverse of theoperations performed at the encoding stages: the first decoder stage 212inverts the third encoder stage 206, the second decoder stage 214inverts the second encoder stage 204 and the third decoder stage 216inverts the first encoder stage 202. The output of the k-th decodingstage o_(k) ^(D) (binary column vector) may be described by themultiplication of a binary transformation matrix M_(k) ^(D)=g_(k)^(D)(i_(k) ^(D)) and a binary partitioning vector n_(k) ^(D)=h_(k)^(D)(i_(k) ^(D)) (binary column vector) that depend on the binary inputi_(k) ^(D) (binary column vector)

o _(k) ^(D) =M _(k) ^(D) n _(k) ^(D) =g _(k) ^(D)(i _(k) ^(d))h _(k)^(D)(i _(k) ^(D))

where the superscript D refers to the decoding operation. Finally,concatenation of decoding stages is done such that the output of thek-th decoding stage, k=1, 2 (in general, k=1, . . . , K−1) is the inputof the next decoding stage, i.e., i_(k+1) ^(D)−o_(k) ^(D).

As will be shown in the section on implementing the rate-16/17 encoderand decoder, the encoder and decoder may be implemented with fewtwo-input gates. All of the Boolean equations for encoding and decodingare the result of multiplication of a specific matrix and a partitioningcolumn vector that are specified in the next two sections.

Matrix-Vector Description of Encoding Stages for Rate-16/17 PRML(G=6,I=7, M=15) Code with Minimum Transition Density

In this section, the encoding of 16 bits to 17 bits, that is thegeneration of codewords of the mother code, is fully described using amatrix-vector notation. A compact representation of all three encodingstages 202, 204, 206 is presented. Sixteen input bits a(1) . . . a(16)are input to the first encoder stage 202, then processed through each ofthe stages described below to produce the 17-bit mother code output bitsy(1) . . . y(17) at the third level encoder output. The final step tocreating the 33-bit or 49-bit codeword is interleaving the 17-bitencoder output with either 16 or 32 uncoded bits. This final step isbriefly described in the last three sections.

Encoding Stage 1:

Input column vector: i₁ ^(E=a) ^(T)=[a₁ a₂ a₁₆]^(T)

Transformation matrix: M₁ ^(E)=g₁ ^(E)(i₁ ^(E))=[M_(1,1) ^(E)M_(1,2)^(E)]

$M_{1,1}^{E} = \begin{bmatrix}a_{9} & a_{1} & a_{1} & a_{1} & a_{1} & a_{1} & a_{9} & a_{1} & a_{5} & a_{5} & a_{5} & a_{5} & a_{1} & a_{1} & a_{1} & a_{1} \\a_{10} & a_{2} & a_{2} & a_{2} & a_{2} & a_{2} & a_{10} & a_{2} & a_{6} & a_{6} & a_{6} & a_{6} & a_{2} & a_{2} & a_{2} & a_{2} \\a_{11} & a_{3} & a_{3} & a_{3} & a_{3} & a_{3} & a_{11} & a_{3} & a_{7} & a_{7} & a_{7} & a_{7} & a_{3} & a_{3} & a_{3} & a_{3} \\a_{12} & a_{4} & a_{4} & a_{4} & a_{4} & a_{4} & a_{12} & a_{4} & a_{8} & a_{8} & a_{8} & a_{8} & a_{4} & a_{4} & a_{4} & a_{4} \\a_{5} & a_{9} & a_{5} & a_{5} & a_{5} & a_{5} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 \\a_{6} & a_{10} & a_{6} & a_{6} & a_{6} & a_{6} & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 \\a_{7} & a_{11} & a_{7} & a_{7} & a_{7} & a_{7} & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 1 \\a_{8} & a_{12} & a_{8} & a_{8} & a_{8} & a_{8} & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 \\0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\0 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\1 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\a_{13} & a_{13} & a_{13} & a_{13} & a_{13} & a_{9} & a_{13} & a_{9} & a_{9} & a_{13} & a_{13} & a_{13} & a_{13} & a_{13} & a_{13} & a_{5} \\a_{14} & a_{14} & a_{14} & a_{14} & a_{14} & a_{10} & a_{14} & a_{10} & a_{10} & a_{14} & a_{14} & a_{14} & a_{14} & a_{14} & a_{14} & a_{6} \\a_{15} & a_{15} & a_{15} & a_{15} & a_{15} & a_{11} & a_{15} & a_{11} & a_{11} & a_{15} & a_{15} & a_{15} & a_{15} & a_{15} & a_{15} & a_{7} \\a_{16} & a_{16} & a_{16} & a_{16} & a_{16} & a_{12} & a_{16} & a_{12} & a_{12} & a_{16} & a_{16} & a_{16} & a_{16} & a_{16} & a_{16} & a_{8}\end{bmatrix}$ $M_{1,2}^{E} = \begin{bmatrix}a_{1} & a_{1} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & a_{1} \\a_{2} & a_{2} & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 1 & a_{2} \\a_{3} & a_{3} & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & a_{3} \\a_{4} & a_{4} & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & a_{4} \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{5} \\0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{6} \\1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & a_{7} \\1 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{8} \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{9} \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{10} \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{11} \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{12} \\a_{5} & a_{5} & a_{9} & a_{13} & a_{13} & a_{13} & a_{5} & a_{5} & a_{5} & a_{1} & a_{1} & a_{1} & 0 & 0 & 0 & a_{13} \\a_{6} & a_{6} & a_{10} & a_{14} & a_{14} & a_{14} & a_{6} & a_{6} & a_{6} & a_{2} & a_{2} & a_{2} & 0 & 0 & 0 & a_{14} \\a_{7} & a_{7} & a_{11} & a_{15} & a_{15} & a_{7} & a_{7} & a_{7} & a_{7} & a_{3} & a_{3} & a_{3} & 1 & 1 & 1 & a_{15} \\a_{8} & a_{8} & a_{12} & a_{16} & a_{16} & a_{16} & a_{8} & a_{8} & a_{8} & a_{4} & a_{4} & a_{4} & 1 & 1 & 1 & a_{16}\end{bmatrix}$

Partitioning column vector: n₁ ^(E)=h₁ ^(E)(i₁ ^(E))=p^(T)=[p₁ p₂ . . .p₃₂]^(T) where the following six auxiliary variables:

v ₁= a ₁ +a ₂ +a ₃ +a ₄

v ₂= a ₅ +a ₆ +a ₇ +a ₈

v ₃= a ₉ +a ₁₀ +a ₁₁ +a ₁₂

v ₄ =ā ₉ +a ₁₀ +ā ₁₁ +ā ₁₂

v ₅ =a ₉ +a ₁₀ +a ₁₁ +a ₁₂

v ₆= a ₁₃ +a ₁₄ +a ₁₅ +a ₁₆

are used to express the components of the partitioning vector:

p₁ = v₁ v ₂ v ₃ v ₄ v ₅ v ₆, p₂ = v ₁v₂ v ₃ v ₄ v ₅ v ₆, p₃ = v ₁ v ₂v₃v ₄ v ₅ v ₆, p₄ = v ₁ v ₂ v ₃v₄ v ₅ v ₆, p₅ = v ₁ v ₂ v ₃ v ₄v₅ v ₆, p₆= v ₁ v ₂ v ₃ v ₄ v ₅v₆, p₇ = v₁v₂ v ₃ v ₄ v ₅ v ₆, p₈ = v ₁v₂ v ₃ v ₄ v₅v₆, p₉ = v₁ v ₂ v ₃ v ₄ v ₅v₆, p₁₀ = v₁ v ₂v₃ v ₄ v ₅ v ₆, p₁₁ = v₁ v ₂v ₃v₄ v ₅ v ₆, p₁₂ = v₁ v ₂ v ₃ v ₄v₅ v ₆, p₁₃ = v ₁v₂v₃ v ₄ v ₅ v ₆,p₁₄ = v ₁v₂ v ₃v₄ v ₅ v ₆, p₁₅ = v ₁v₂ v ₃ v ₄v₅ v ₆, p₁₆ = v ₁ v ₂v₃ v₄ v ₅v₆, p₁₇ = v ₁ v ₂ v ₃v₄ v ₅v₆, p₁₈ = v ₁ v ₂ v ₃ v ₄v₅v₆, p₁₉ =v₁v₂ v ₃ v ₄ v ₅v₆, p₂₀ = v₁v₂v₃ v ₄ v ₅ v ₆, p₂₁ = v₁v₂ v ₃v₄ v ₅ v ₆,p₂₂ = v₁v₂ v ₃ v ₄v₅ v ₆, p₂₃ = v₁ v ₂v₃ v ₄ v ₅v₆, p₂₄ = v₁ v ₂ v ₃v₄ v₅v₆, p₂₅ = v₁ v ₂ v ₃ v ₄v₅v₆, p₂₆ = v ₁v₂v₃ v ₄ v ₅v₆, p₂₇ = v ₁v₂ v₃v₄ v ₅v₆, p₂₈ = v ₁v₂ v ₃ v ₄v₅v₆, p₂₉ = v₁v₂v₃ v ₄ v ₅v₆, p₃₀ = v₁v₂ v₃v₄ v ₅v₆, p₃₁ = v₁v₂ v ₃ v ₄v₅v₆, p₃₂ = v ₁ v ₂ v ₃ v ₄ v ₅ v ₆,

Output column vector: o₁ ^(E)=M₁ ^(E)n₁ ^(E)=b^(T)=[b¹ b₂ . . . b₁₇]^(T)

Encoding Stage 2:

Input column vector: i₂ ^(E)=b^(T)=[b₁ b₂ . . . b₁₇]^(T)

Transformation matrix: M₂ ^(E)=g₂ ^(E)(i₂ ^(E))

$M_{2}^{E} = \begin{bmatrix}b_{2} & 0 & b_{4} & b_{14} & b_{6} & b_{10} & b_{8} & b_{12} & b_{9} & 0 & b_{11} & 0 & b_{12} & 1 & b_{15} & b_{16} & b_{17} \\b_{14} & 1 & b_{9} & b_{15} & b_{11} & b_{10} & b_{13} & b_{12} & b_{1} & 0 & b_{3} & 0 & b_{5} & 1 & b_{7} & b_{16} & b_{17} \\b_{14} & b_{15} & 1 & b_{9} & b_{10} & b_{11} & b_{12} & b_{13} & 1 & 1 & 1 & 1 & 1 & 0 & 1 & b_{16} & b_{17} \\b_{1} & b_{2} & b_{3} & b_{4} & b_{5} & b_{6} & b_{7} & b_{8} & b_{9} & b_{10} & b_{11} & b_{12} & b_{13} & b_{14} & b_{15} & b_{16} & b_{17}\end{bmatrix}^{T}$

Partitioning column vector: n₂ ^(E)=h₂ ^(E)(i₂ ^(E))=q^(T)=[q₁ q₂ q₃q₄]^(T) where

q ₁= b ₁ +b ₃ +b ₅ +b ₇

q ₂= b ₂ +b ₄ +b ₆ +b ₈

q₃=b₁b₂b₃b₄b₅b₆b₇b₈

q ₄= q ₁ +q ₂ +q ₃

Output column vector: o₂ ^(E)=M₂ ^(E)n₂ ^(E)=C^(T)=[c₁ c₂ . . . c₁₇]^(T)

Encoding Stage 3:

Input column vector: i₃ ^(E)=c^(T)=[c₁ c₂ . . . c₁₇]^(T)

Transformation matrix: M₃E=g₃E(i₃E)

${M_{3}^{E}\begin{bmatrix}c_{10} & c_{12} & 1 & 1 & 0 & 0 & 0 & 0 & c_{9} & 1 & c_{11} & 0 & c_{13} & c_{14} & c_{15} & c_{16} & c_{17} \\c_{1} & c_{2} & c_{3} & c_{4} & c_{5} & c_{6} & 1 & 1 & 0 & c_{7} & 0 & c_{8} & 0 & 1 & 1 & 0 & 1 \\c_{1} & c_{2} & c_{3} & c_{4} & c_{5} & c_{6} & c_{7} & c_{8} & c_{9} & c_{10} & c_{11} & c_{12} & c_{13} & c_{14} & c_{15} & c_{16} & c_{17}\end{bmatrix}}^{T}$

Partitioning column vector: n₃ ^(E)=h₃ ^(E)=h₃ ^(E)(i₃ ^(E))=u^(T)=[u₁u₂u₃]^(T) where

u₁= c ₁ c ₂ c ₃c₄c₅ c ₆ c ₇ c ₈

u₂= c ₉ c ₁₀ c ₁₁ c ₁₂c₁₃c₁₄ c ₁₅ c ₁₆ c ₁₇

u ₃= u ₁ +u ₂

Output column vector: o₃ ^(E)=M₃ ^(E)n₃ ^(E)=y^(T)=[y₁ y₂ . . . y₁₇]T

Matrix-Vector Description of Decoding Stages for Rate-16/17 PRML(G=6,1=7, M=15) Code with Minimum Transition Density

In this section, decoding 17-bits to 16-bits is described usingmatrix-vector notation. A compact representation of all three decodingstages 212, 214, 216 is presented. Seventeen input bits z(1) . . . z(17)are input to the first decoder stage 212, then processed through each ofthe stages described below to produce the 16-bit output bits f(1) . . .f(16) at the output f of the third decoder stage 216. The final step tocreating the 32-bit or 48-bit dataword is interleaving the 16-bit outputof the decoder 210 with either 16 or 32 uncoded bits. This final step isbriefly described in the last three sections.

Decoding Stage 1:

Input column vector: i₁ ^(D)=z^(T)=[z₁ z₂ . . . z₁₇]^(T)

Transformation matrix: M₁ ^(D)=g₁ ^(D)(i₁ ^(D))

$M_{1}^{D} = \begin{bmatrix}0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & z_{9} & z_{1} & z_{11} & z_{2} & z_{13} & z_{14} & z_{15} & z_{16} & z_{17} \\z_{1} & z_{2} & z_{3} & z_{4} & z_{5} & z_{6} & z_{10} & z_{12} & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 \\z_{1} & z_{2} & z_{3} & z_{4} & z_{5} & z_{6} & z_{7} & z_{8} & z_{9} & z_{10} & z_{11} & z_{12} & z_{13} & z_{14} & z_{15} & z_{16} & z_{17}\end{bmatrix}^{T}$

Partitioning column vector: n₁ ^(D)=h₁ ^(D)(i₁ ^(D))=w′=[w₁ w₂ w₃]^(T)where

w₁=z₃z₄ z ₅ z ₆ z ₇ z ₈ z ₁₀ z ₁₂

w₂=z₇z₈ z ₉ z ₁₁ z ₁₃z₁₄z₁₅ z ₁₆z₁₇

w ₃= w ₁ +w ₂

Output column vector: o₁ ^(D)=M₁ ^(D)n₁ ^(D)=d^(T)=[d₁ d₂ . . . d₁₇]^(T)

Decoding Stage 2:

Input column vector: i₂ ^(D)=d^(T)=[d₁ d₂ . . . d₁₇]^(T)

Transformation matrix: M₂ ^(D)=g₂ ^(D)(i₂ ^(D))

$M_{2}^{D} = \begin{bmatrix}0 & d_{1} & 0 & d_{3} & 0 & d_{5} & 0 & d_{7} & d_{9} & d_{6} & d_{11} & d_{8} & d_{13} & d_{4} & d_{15} & d_{16} & d_{17} \\d_{9} & 0 & d_{11} & 0 & d_{13} & 0 & d_{15} & 0 & d_{3} & d_{6} & d_{5} & d_{8} & d_{7} & d_{1} & d_{4} & d_{16} & d_{17} \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & d_{4} & d_{5} & d_{6} & d_{7} & d_{8} & d_{1} & d_{2} & d_{16} & d_{17} \\d_{1} & d_{2} & d_{3} & d_{4} & d_{5} & d_{6} & d_{7} & d_{8} & d_{9} & d_{10} & d_{11} & d_{12} & d_{13} & d_{14} & d_{15} & d_{16} & d_{17}\end{bmatrix}^{T}$

Partitioning column vector: n₂ ^(D)=h₂ ^(D)(i₂ ^(D))=r^(T)=[r₁ r₂ r₃r₄]^(T) where

r₁= d ₂ d ₁₀ d ₁₂d₁₄

r₂=d₂ d ₁₀ d ₁₂d₁₄

r₃=d₃d₉d₁₀d₁₁d₁₂d₁₃ d ₁₄d₁₅

r ₄= r ₁ +r ₂ +r ₃

Output column vector: o₂ ^(D)=M₂ ^(D)n₂ ^(D)=e^(T)=[e₁ e₂ . . . e₁₇]^(T)

Decoding Stage 3:

Input column vector: i₃ ^(D)=e^(T)=[e₁ e₂ . . . e₁₇]^(T)

Transformation matrix: M₃ ^(D)=g₃ ^(D)(i₃ ^(D))=[M_(3,1) ^(D) M_(3,2)^(D)]

$M_{3,1}^{D} = \begin{bmatrix}0 & e_{1} & e_{1} & e_{1} & e_{1} & e_{1} & 0 & e_{1} & 0 & 0 & 0 & 0 & e_{1} & e_{1} & e_{1} & e_{1} \\0 & e_{2} & e_{2} & e_{2} & e_{2} & e_{2} & 0 & e_{2} & 0 & 0 & 0 & 0 & e_{2} & e_{2} & e_{2} & e_{2} \\0 & e_{3} & e_{3} & e_{3} & e_{3} & e_{3} & 0 & e_{3} & 0 & 0 & 0 & 0 & e_{3} & e_{3} & e_{3} & e_{3} \\0 & e_{4} & e_{4} & e_{4} & e_{4} & e_{4} & 0 & e_{4} & 0 & 0 & 0 & 0 & e_{4} & e_{4} & e_{4} & e_{4} \\e_{5} & e_{5} & e_{5} & e_{5} & e_{5} & e_{5} & 0 & 0 & e_{1} & e_{1} & e_{1} & e_{1} & 0 & 0 & 0 & e_{14} \\e_{6} & e_{6} & e_{6} & e_{6} & e_{6} & e_{6} & 0 & 0 & e_{2} & e_{2} & e_{2} & e_{2} & 0 & 0 & 0 & e_{15} \\e_{7} & e_{7} & e_{7} & e_{7} & e_{7} & e_{7} & 0 & 0 & e_{3} & e_{3} & e_{3} & e_{3} & 0 & 0 & 0 & e_{16} \\e_{8} & e_{8} & e_{8} & e_{8} & e_{8} & e_{8} & 0 & 0 & e_{4} & e_{4} & e_{4} & e_{4} & 0 & 0 & 0 & e_{17} \\e_{1} & e_{5} & 0 & 0 & 1 & e_{14} & e_{1} & e_{14} & e_{14} & 0 & 0 & 1 & 0 & 0 & 1 & 0 \\e_{2} & e_{6} & 0 & 1 & 1 & e_{15} & e_{2} & e_{15} & e_{15} & 0 & 1 & 1 & 0 & 1 & 1 & 0 \\e_{3} & e_{7} & 0 & 0 & 1 & e_{16} & e_{3} & e_{16} & e_{16} & 0 & 0 & 1 & 0 & 0 & 1 & 0 \\e_{4} & e_{8} & 0 & 0 & 1 & e_{17} & e_{4} & e_{17} & e_{17} & 0 & 0 & 1 & 0 & 0 & 1 & 0 \\e_{14} & e_{14} & e_{14} & e_{14} & e_{14} & 0 & e_{14} & 0 & 0 & e_{14} & e_{14} & e_{14} & e_{14} & e_{14} & e_{14} & 0 \\e_{15} & e_{15} & e_{15} & e_{15} & e_{15} & 0 & e_{15} & 0 & 0 & e_{15} & e_{15} & e_{15} & e_{15} & e_{15} & e_{15} & 0 \\e_{16} & e_{16} & e_{16} & e_{16} & e_{16} & 0 & e_{16} & 0 & 0 & e_{16} & e_{16} & e_{16} & e_{16} & e_{16} & e_{16} & 0 \\e_{17} & e_{17} & e_{17} & e_{17} & e_{17} & 0 & e_{17} & 0 & 0 & e_{17} & e_{17} & e_{17} & e_{17} & e_{17} & e_{17} & 0\end{bmatrix}$ $M_{3,2}^{D} = \begin{bmatrix}e_{1} & e_{1} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & e_{14} & e_{14} & e_{14} & 0 & 0 & 0 & e_{1} \\e_{2} & e_{2} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & e_{15} & e_{15} & e_{15} & 0 & 0 & 0 & e_{2} \\e_{3} & e_{3} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & e_{16} & e_{16} & e_{16} & 0 & 0 & 0 & e_{3} \\e_{4} & e_{4} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & e_{17} & e_{17} & e_{17} & 0 & 0 & 0 & e_{4} \\e_{14} & e_{14} & 0 & 0 & 0 & 0 & e_{14} & e_{14} & e_{14} & 0 & 0 & 0 & 0 & 0 & 0 & e_{5} \\e_{15} & e_{15} & 0 & 0 & 0 & 0 & e_{15} & e_{15} & e_{15} & 0 & 0 & 0 & 0 & 0 & 0 & e_{6} \\e_{16} & e_{16} & 0 & 0 & 0 & 0 & e_{16} & e_{16} & e_{16} & 0 & 0 & 0 & 0 & 0 & 0 & e_{7} \\e_{17} & e_{17} & 0 & 0 & 0 & 0 & e_{17} & e_{17} & e_{17} & 0 & 0 & 0 & 0 & 0 & 0 & e_{8} \\0 & 1 & e_{14} & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & e_{9} \\1 & 1 & e_{15} & 0 & 1 & 1 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 1 & 1 & e_{10} \\0 & 1 & e_{16} & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & e_{11} \\0 & 1 & e_{17} & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & e_{13} \\0 & 0 & 0 & e_{14} & e_{14} & e_{14} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & e_{14} \\0 & 0 & 0 & e_{15} & e_{15} & e_{15} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & e_{15} \\0 & 0 & 0 & e_{16} & e_{16} & e_{16} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & e_{16} \\0 & 0 & 0 & e_{17} & e_{17} & e_{17} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & e_{17}\end{bmatrix}$

Partitioning column vector: n₃ ^(D)=h₃ ^(D)(i_(D) ³)=s^(T)=[s₁ s₂ . . .s₃₂]^(T) where

${s_{1} = {{\overset{\_}{e}}_{9}e_{10}{\overset{\_}{e}}_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{2} = {{\overset{\_}{e}}_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}{\overset{\_}{e}}_{13}}},{s_{3} = {{\overset{\_}{e}}_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{4} = {e_{9}e_{10}{\overset{\_}{e}}_{11}{\overset{\_}{e}}_{12}{\overset{\_}{e}}_{13}}},{s_{5} = {e_{9}e_{10}{\overset{\_}{e}}_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{6} = {e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}{\overset{\_}{e}}_{13}}},{s_{7} = {{\overset{\_}{e}}_{5}{\overset{\_}{e}}_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{8} = {{\overset{\_}{e}}_{5}{\overset{\_}{e}}_{6}e_{7}{\overset{\_}{e}}_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{9} = {{\overset{\_}{e}}_{5}{\overset{\_}{e}}_{6}e_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{10} = {{\overset{\_}{e}}_{5}e_{6}{\overset{\_}{e}}_{7}{\overset{\_}{e}}_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{11} = {{\overset{\_}{e}}_{5}e_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{12} = {{\overset{\_}{e}}_{5}e_{6}e_{7}{\overset{\_}{e}}_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{13} = {{\overset{\_}{e}}_{5}e_{6}e_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{14} = {e_{5}{\overset{\_}{e}}_{6}{\overset{\_}{e}}_{7}{\overset{\_}{e}}_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{15} = {e_{5}{\overset{\_}{e}}_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{16} = {e_{5}{\overset{\_}{e}}_{6}e_{7}{\overset{\_}{e}}_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{17} = {e_{5}{\overset{\_}{e}}_{6}e_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{18} = {e_{5}e_{6}{\overset{\_}{e}}_{7}{\overset{\_}{e}}_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{19} = {{\overset{\_}{e}}_{1}{\overset{\_}{e}}_{2}{\overset{\_}{e}}_{3}e_{4}e_{5}e_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{20} = {{\overset{\_}{e}}_{1}{\overset{\_}{e}}_{2}e_{3}{\overset{\_}{e}}_{4}e_{5}e_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{21} = {{\overset{\_}{e}}_{1}e_{2}{\overset{\_}{e}}_{3}{\overset{\_}{e}}_{4}e_{5}e_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{22} = {{\overset{\_}{e}}_{1}e_{2}{\overset{\_}{e}}_{3}{\overset{\_}{e}}_{4}e_{5}e_{6}e_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{23} = {{\overset{\_}{e}}_{1}e_{2}{\overset{\_}{e}}_{3}e_{4}e_{5}e_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{24} = {{\overset{\_}{e}}_{1}e_{2}e_{3}{\overset{\_}{e}}_{4}e_{5}e_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{25} = {{\overset{\_}{e}}_{1}e_{2}e_{3}e_{4}e_{5}e_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{26} = {e_{1}{\overset{\_}{e}}_{2}{\overset{\_}{e}}_{3}{\overset{\_}{e}}_{4}e_{5}e_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{27} = {e_{1}{\overset{\_}{e}}_{2}{\overset{\_}{e}}_{3}e_{4}e_{5}e_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{28} = {e_{1}{\overset{\_}{e}}_{2}e_{3}{\overset{\_}{e}}_{4}e_{5}e_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{29} = {e_{1}{\overset{\_}{e}}_{2}e_{3}e_{4}e_{5}e_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{30} = {e_{1}e_{2}{\overset{\_}{e}}_{3}{\overset{\_}{e}}_{4}e_{5}e_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{31} = {e_{1}e_{2}{\overset{\_}{e}}_{3}e_{4}e_{5}e_{6}{\overset{\_}{e}}_{7}e_{8}e_{9}e_{10}e_{11}{\overset{\_}{e}}_{12}e_{13}}},{s_{32} = \overset{\_}{{\sum\limits_{i = 1}^{31}s_{i}},}}$

Output column vector: o₃ ^(D)=M₃ ^(D)n₃ ^(D)=f^(T)=[f₁ f₂ . . . f₁₆]^(T)

Boolean Logic for Rate-16/17 PRML(G=6, I=7, M=15) Encoder

The encoding of 16-bits to 17-bits to generate the mother code inaccordance with the present invention is completely described by thefollowing MATLAB Boolean operations. Sixteen inputs bits a(1) . . .a(16) are input to a first encoder stage 202, then processed througheach of the following stages described below to produce the 17-bitmother code output bits y(1) . . . y(17) at the third level encoderoutput. The final step to creating the 33-bit or 49-bit codeword isinterleaving the 17-bit encoder output with either 16 or 32 uncoded bitsand is briefly described in the last three sections. The followingBoolean equations describe the first encoder stage 202 with 16-bit inputa and 17-bit output b.

Auxiliary Boolean variables:

v1=˜(a(1)|a(2)|a(3)|a(4))

v2=˜(a(5)|a(6)|a(7)|a(8))

v3=˜(a(9)|a(10)|a(11)|a(12))

v4=˜a(9)&a(10)&˜a(11)&˜a(12)

v5=a(9)&a(10)&a(11)&a(12)

v6=˜(a(13)|a(14)|a(15)|a(16))

First-stage partitions:

p(1)=v1&˜v2&˜v3&˜v4&˜v5&˜v6

p(2)=˜v1&v2&˜v3&˜v4&˜v5&˜v6

p(3)=˜v1&˜v2&v3&˜v4&˜v5&˜v6

p(4)=˜v1&˜v2&˜v3&v4&˜v5&˜v6

p(5)=˜v1&˜v2&˜v3&˜v4&v5&˜v6

p(6)=˜v1&˜v2&˜v3&˜v4&˜v5&v6

p(7)=v1&v2&˜v3&˜v4&˜v5&˜v6

p(8)=˜v1&v2&˜v3&˜v4&˜v5&v6

p(9)=v1&˜v2&˜v3&˜v4&˜v5&v6

p(10)=v1&˜v2&v3&˜v4&˜v5&˜v6

p(11)=v1&˜v2&˜v3&v4&˜v5&˜v6

p(12)=v1&˜v2&˜v3&˜v4&v5&˜v6

p(13)=˜v1&v2&v3&˜v4&˜v5&˜v6

p(14)=˜v1&v2&˜v3&v4&˜v5&˜v6

p(15)=˜v1&v2&˜v3&˜v4&v5&˜v6

p(16)=˜v1&˜v2&v3&˜v4&˜v5&v6

p(17)=˜v1&˜v2&˜v3&v4&˜v5&v6

p(18)=˜v1&˜v2&˜v3&˜v4&v5&v6

p(19)=v1&v2&˜v3&˜v4&˜v5&v6

p(20)=v1&v2&v3&˜v4&˜v5&˜v6

p(21)=v1&v2&˜v3&v4&˜v5&˜v6

p(22)=v1&v2&˜v3&˜v4&v5&˜v6

p(23)=v1&˜v2&v3&˜v4&˜v5&v6

p(24)=v1&˜v2&˜v3&v4&˜v5&v6

p(25)=v1&˜v2&˜v3&˜v4&v5&v6

p(26)=˜v1&v2&v3&˜v4&˜v5&v6

p(27)=˜v1&v2&˜v3&v4&˜v5&v6

p(28)=˜v1&v2&˜v3&˜v4&v5&v6

p(29)=v1&v2&v3&˜v4&˜v5&v6

p(30)=v1&v2&˜v3&v4&˜v5&v6

p(31)=v1&v2&˜v3&˜v4&v5&v6

p(32)=˜v1&˜v2&˜v3&˜v4&˜v5&˜v6

Auxiliary Boolean variables:

v7=p(1)|p(7)

v8=p(2)|p(3)|p(4)|p(5)|p(6)|p(8)|p(13)|p(14)|p(15)|p(16)|p(17)|p(18)|p(32)

v9=p(9)|p(10)|p(11)|p(12)

v10=p(1)|p(3)|p(4)|p(5)|p(6)|p(32)

v11=p(14)|p(15)|p(16)|p(17)|p(18)

v12=p(19)|p(20)|p(21)|p(22)|p(23)|p(24)|p(25)|p(26)|p(27)|p(28)|p(29)|p(30)|p(31)

v13=p(10)|p(11)|p(12)|p(13)

v14=p(7)|p(8)|v9|p(13)|v11|v12

v15=p(1)|p(2)|p(3)|p(4)|p(5)|p(7)|p(10)|p(11)|p(12)|p(13)|p(14)|p(15)|p(20)|p(21)|p(22)|p(32)

v16=p(6)|p(8)|p(9)|p(19)

v17=p(16)|p(17)|p(18)|p(23)|p(24)|p(25)

v18=p(26)|p(27)|p(28)

v19=p(29)|p(30)|p(31)

First-stage encoding output:

b(1)=a(9)&v7|a(1)&v8|a(5)&v9|p(26)|p(27)|p(28)|p(29)|p(30)|p(31)

b(2)=a(10)&v7|a(2)&v8|a(6)&v9|p(22)|p(23)|p(24)|p(25)|p(30)|p(31)

b(3)=a(11)&v7|a(3)&v8|a(7)&v9|p(20)|p(21)|p(24)|p(25)|p(28)|p(29)

b(4)=a(12)&v7|a(4)&v8|a(8)&v9|p(19)|p(21)|p(23)|p(25)|p(27)|p(29)|p(31)

b(5)=a(5)&v10|a(9)&p(2)|v11|v12

b(6)=a(6)&v10|a(10)&p(2)|v13|p(18)|v12

b(7)=a(7)&v10|a(11)&p(2)|p(8)|p(9)|p(12)|p(13)|p(16)|p(17)

b(8)=a(8)&v10|a(12)&p(2)|p(7)|p(9)|p(11)|p(13)|p(15)|p(17)|v12

b(9)=a(9)&p(32)|p(4)|p(5)|p(6)|v14

b(10)=a(10)&p(32)|p(1)|p(2)|p(3)|p(4)|p(5)|p(6)|v14

b(11)=a(11)&p(32)|p(2)|p(3)|p(6)|v14

b(12)=p(32)

b(13)=a(12)&p(32)|p(1)|p(3)|p(5)|v14

b(14)=a(13)&v15|a(9)&v16|a(5)&v17|a(1)&v18

b(15)=a(14)&v15|a(10)&v16|a(6)&v17|a(2)&v18

b(16)=a(15)&v15|a(11)&v16|a(7)&v17|a(3)&v18|v19

b(17)=a(16)&v15|a(12)&v16|a(8)&v17|a(4)&v18|v19

The following Boolean equations describe the second encoder stage 204with 17-bit input b and 17-bit output c.

Second-Stage Partitions:

q(1)=˜(b(1)|b(3)|b(5)|b(7))

q(2)=˜(b(2)|b(4)|b(6)|b(8))

q(3)=b(1)&b(2)&b(3)&b(4)&b(5)&b(6)&b(7)&b(8)

q(4)=˜(q(1)|q(2)|q(3))

Second-stage encoder remapping output:

c(1)=b(2)&q(1)|b(14)&q(2)|b(14)&q(3)|b(1)&q(4)

c(2)=q(2)|b(15)&q(3)|b(2)&q(4)

c(3)=b(4)&q(1)|b(9)&q(2)|q(3)|b(3)&q(4)

c(4)=b(14)&q(1)|b(15)&q(2)|b(9)&q(3)|b(4)&q(4)

c(5)=b(6)&q(1)|b(11)&q(2)|b(10)&q(3)|b(5)&q(4)

c(6)=b(10)&q(1)|b(10)&q(2)|b(11)&q(3)|b(6)&q(4)

c(7)=b(8)&q(1)|b(13)&q(2)|b(12)&q(3)|b(7)&q(4)

c(8)=b(12)&q(1)|b(12)&q(2)|b(13)&q(3)|b(8)&q(4)

c(9)=b(9)&q(1)|b(1)&q(2)|q(3)|b(9)&q(4)

c(10)=q(3)|b(10)&q(4)

c(11)=b(11)&q(1)|b(3)&q(2)|q(3)|b(11)&q(4)

c(12)=q(3)|b(12)&q(4)

c(13)=b(13)&q(1)|b(5)&q(2)|q(3)|b(13)&q(4)

c(14)=q(1)|q(2)|b(14)&q(4)

c(15)=b(15)&q(1)|b(7)&q(2)|q(3)|b(15)&q(4)

c(16)=b(16)&q(1)|b(16)&q(2)|b(16)&q(3)|b(16)&q(4)

c(17)=b(17)&q(1)|b(17)&q(2)|b(17)&q(3)|b(17)&q(4)

The following Boolean equations describe the third encoder stage 206with 17-bit input c and 17-bit output y.

Third-stage partitions:

u(1)=˜c(1)&˜c(2)&˜c(3)&c(4)&c(5)&˜c(6)&˜c(7)&˜c(8)

u(2)=˜c(9)&˜c(10)&˜c(11)&˜c(12)&c(13)&c(14)&˜c(15)&˜c(16)&˜c(17)

u(3)=˜(u(1)|u(2))

Auxiliary Boolean variables:

v20=u(2)|u(3)

v21=u(1)|u(3)

Third-stage encoder remapping output (encoder output):

y(1)=c(10)&u(1)|c(1)&v20

y(2)=c(12)&u(1)|c(2)&v20

y(3)=u(1)|c(3)&v20

y(4)=u(1)|c(4)&v20

y(5)=c(5)&v20

y(6)=c(6)&v20

y(7)=u(2)|c(7)&u(3)

y(8)=u(2)|c(8)&u(3)

y(9)=c(9)&v21

y(10)=u(1)|c(7)&u(2)|c(10)&u(3)

y(1)=c(11)&v21

y(12)=c(8)&u(2)|c(12)&u(3)

y(13)=c(13)&v21

y(14)=c(14)&v21|u(2)

y(15)=c(15)&v21|u(2)

y(16)=c(16)&v21

y(17)=c(17)&v21|u(2)

Boolean Logic for Rate-16/17 PRML(G=6, I=7, M=15) Decoder

The following Boolean equations describe the first decoder stage 212with 17-bit input z and 17-bit output d. The first decoder stage 212inverts the third encoder stage 206.

First-stage decoder partitions:

w(1)=z(3)&z(4)&˜z(5)&˜z(6)&˜z(7)&˜z(8)&z(10)&˜z(12)

w(2)=z(7)&z(8)&˜z(9)&˜z(11)&˜z(13)&z(14)&z(15)&˜z(16)&z(17)

w(3)=˜(w(1)|w(2))

Auxiliary Boolean variables:

t2=w(2)|w(3)

t2=w(1)|w(3)

First-stage decoder remapping output:

d(1)=z(1)&t1

d(2)=z(2)&t1

d(3)=z(3)&t1

d(4)=w(1)|z(4)&t1

d(5)=w(1)|z(5)&t1

d(6)=z(6)&t1

d(7)=z(10)&w(2)|z(7)&w(3)

d(8)=z(12)&w(2)|z(8)&w(3)

d(9)=z(9)&t2

d(10)=z(1)&w(1)|z(10)&w(3)

d(11)=z(11)&t2

d(12)=z(2)&w(1)|z(12)&w(3)

d(13)=z(13)&t2|w(2)

d(14)=z(14)&t2|w(2)

d(15)=z(15)&t2

d(16)=z(16)&t2

d(17)=z(17)&t2

The following Boolean equations describe the second decoder stage 214with 17-bit input d and 17-bit output e. The second decoder stage 214inverts the second encoder stage 204.

Second-stage decoder partitions:

r(1)=˜d(2)&˜d(10)&˜d(12)&d(14)

r(2)=d(2)&˜d(110)&˜d(12)&d(14)

r(3)=d(3)&d(9)&d(110)&d(1)&d(12)&d(13)&˜d(14)&d(15)

r(4)=˜(r(1)|r(2)|r(3))

Auxiliary Boolean variables:

t3=r(1)|r(4)

t4=r(1)|r(2)

Second-stage decoder remapping output:

e(1)=d(9)&r(2)|r(3)|d(1)&r(4)

e(2)=d(1)&r(1)|r(3)|d(2)&r(4)

e(3)=d(11)&r(2)|r(3)|d(3)&r(4)

e(4)=d(3)&r(1)|r(3)|d(4)&r(4)

e(5)=d(13)&r(2)|r(3)|d(5)&r(4)

e(6)=d(5)&r(1)|r(3)|d(6)&r(4)

e(7)=d(15)&r(2)|r(3)|d(7)&r(4)

e(8)=d(7)&r(1)|r(3)|d(8)&r(4)

e(9)=d(9)&t3|d(3)&r(2)|d(4)&r(3)

e(110)=d(6)&t4|d(5)&r(3)|d(10)&r(4)

e(11)=d(11)&t3|d(5)&r(2)|d(6)&r(3)

e(12)=d(8)&t4|d(7)&r(3)|d(12)&r(4)

e(13)=d(13)&t3|d(7)&r(2)|d(8)&r(3)

e(14)=d(4)&r(1)|d(1)&(r(2)|r(3))|d(14)&r(4)

e(15)=d(15)&t3|d(4)&r(2)|d(2)&r(3)

e(16)=d(16)

e(17)=d(17)

The following Boolean equations describe the third (last) decoding stagewith 17-bit input e and 16-bit output f. The third decoder stage 216inverts the first encoder stage 202. In the absence of channel errors,the 16-bit encoder input is equal to the 16-bit decoder output, i.e.,a=f.

Auxiliary Boolean variables:

t5=e(9)&e(10)&e(11)&˜e(12)&e(13)

t6=e(5)&e(6)&˜e(7)&e(8)&t5

Third-stage decoder partitions:

s(1)=˜e(9)&e(10)&˜e(11)&˜e(12)&e(13)

s(2)=˜e(9)&e(10)&e(11)&˜e(12)&˜e(13)

s(3)=˜e(9)&e(10)&e(11)&˜e(12)&e(13)

s(4)=e(9)&e(10)&˜e(11)&˜e(12)&˜e(13)

s(5)=e(9)&e(10)&˜e(11)&˜e(12)&e(13)

s(6)=e(9)&e(10)&e(11)&˜e(12)&˜e(13)

s(7)=˜e(5)&˜e(6)&˜e(7)&e(8)&t5

s(8)=˜e(5)&˜e(6)&e(7)&˜e(8)&t5

s(9)=˜e(5)&˜e(6)&e(7)&e(8)&t5

s(10)=˜e(5)&e(6)&˜e(7)&˜e(8)&t5

s(11)=e(5)&e(6)&˜e(7)&e(8)&t5

s(12)=˜e(5)&e(6)&e(7)&˜e(8)&t5

s(13)=˜e(5)&e(6)&e(7)&e(8)&t5

s(14)=e(5)&˜e(6)&˜e(7)&˜e(8)&t5

s(15)=e(5)&˜e(6)&˜e(7)&e(8)&t5

s(16)=e(5)&˜e(6)&e(7)&˜e(8)&t5

s(17)=e(5)&˜e(6)&e(7)&e(8)&t5

s(18)=e(5)&e(6)&˜e(7)&˜e(8)&t5

s(19)=˜e(1)&e(2)&˜e(3)&e(4)&t6

s(20)=˜e(1)&˜e(2)&e(3)&˜e(4)&t6

s(21)=e(1)&e(2)&e(3)&e(4)&t6

s(22)=˜e(1)&e(2)&˜e(3)&˜e(4)&t6

s(23)=˜e(1)&e(2)&˜e(3)&e(4)&t6

s(24)=˜e(1)&e(2)&e(3)&˜e(4)&t6

s(25)=˜e(1)&e(2)&e(3)&e(4)&t6

s(26)=e(1)&˜e(2)&˜e(3)&˜e(4)&t6

s(27)=e(1)&˜e(2)&˜e(3)&e(4)&t6

s(28)=e(1)&˜e(2)&e(3)&˜e(4)&t6

s(29)=e(1)&˜e(2)&e(3)&e(4)&t6

s(30)=e(1)&e(2)&˜e(3)&˜e(4)&t6

s(31)=e(1)&e(2)&˜e(3)&e(4)&t6

Auxiliary Boolean variables:

t7=s(3)|s(4)|s(5)

t8=s(6)|t7

t9=s(10)|s(11)|s(12)

t10=s(13)|s(14)|s(15)

t11=s(16)|s(17)|s(18)

t12=s(20)|s(21)|s(22)

t13=s(23)|s(24)|s(25)

t14=s(26)|s(27)|s(28)

t15=s(1)|s(7)

Last third-stage decoder partition:

s(32)=˜(t15|s(2)|t8|s(8)|s(9)|t9|t10|t11|s(19)|t12|t13|t14|s(29)|s(30)|s(31))

Auxiliary Boolean variables:

t16=s(2)|t8|s(8)|t10|t11|s(32)

t17=s(1)|t8|s(32)

t18=s(9)|t9

t19=t11|t13

t20=s(6)|s(8)|s(9)|s(19)

t21=s(5)|s(12)|s(15)|s(18)|s(22)|s(25)|s(28)|s(31)

t22=t15|s(2)|t7|t9|t10|t12|s(32)

Third-stage decoding output (decoder output):

f(1)=e(1)&t16|e(14)&t14

f(2)=e(2)&t16|e(15)&t14

f(3)=e(3)&t16|e(16)&t14

f(4)=e(4)&t16|e(17)&t14

f(5)=e(5)&t17|e(1)&t18|e(14)&t19

f(6)=e(6)&t17|e(2)&t18|e(15)&t19

f(7)=e(7)&t17|e(3)&t18|e(16)&t19

f(8)=e(8)&t17|e(4)&t18|e(17)&t19

f(9)=e(1)&t15|e(5)&s(2)|t21|e(14)&t20|e(9)&s(32)

f(10)=e(2)&t15|e(6)&s(2)|t21|e(15)&t20|e(10)&s(32)|s(4)|s(11)|s(14)|s(17)|s(21)|s(24)|s(27)|s(30)

f(11)=e(3)&t15|e(7)&s(2)|t21|e(16)&t20|e(11)&s(32)

f(12)=e(4)&t15|e(8)&s(2)|t21|e(17)&t20|e(13)&s(32)

f(13)=e(14)&t22

f(14)=e(15)&t22

f(15)=e(16)&t22

f(16)=e(17)&t22

The encoder and the decoder may be implemented with a total of 936two-input AND and OR gates (559 two-input AND gates and 377 two-input ORgates).

Rate-32/33 PRML(G=14, I=11, M=23) Code (RLL 1)

In one embodiment of a rate-32/33 PRML code of the present invention,m=32, n=16, s=8, Q₁=2, P₁=4, P₂=2 and P₃=2. The rate-16/17 PRML(G=6,I=7, M=15) mother code with minimum transition density Q₂=4 may be usedto obtain a rate-32/33 PRML(G=14, I=11, M=23) code by breaking thecodewords into P₃=2 pieces (8 bits and 9 bits) and inserting (m−n)/s=2uncoded bytes in between (a coded block of 8 bits or 9 bits is alwayspreceded and followed by an uncoded byte). m and n are both integermultiples of the ECC symbol size s. The rate-16/17 PRML(G=6, I=7, M=15)codewords have either interleaved NRZI representation (not precoded),NRZI representation (1/(1⊕D) precoded) or NRZ representation (1/(1⊕D²)precoded) for multiplexing with unencoded data. If the rate-16/17PRML(G=6, I=7, M=15) codewords are in interleaved NRZI, NRZI or NRZ formthen the rate-32/33 PRML code obtained after multiplexing with unencodeddata is in interleaved NRZI, NRZI or NRZ form, respectively. In otherwords, coded data is always precoded using a 1/(1⊕D²) precoder. However,uncoded data can be either not precoded at all, 1/(1⊕D) precoded or1/(1⊕D²) precoded. From an error-rate performance viewpoint, it ispreferable to not use any precoding for the uncoded data. However,because 1/(1⊕D) precoding is already used in conjunction with writeequalization in LTO 1-4, it may be therefore more desirable to use1/(1⊕D) precoding.

FIG. 4 illustrates the process by which a 32-bit input, comprising fours=8-bit error correction coding (ECC) symbols B0(1:8), B1(1:8), B2(1:8),B3(1:8), is transformed into a 33-bit codeword C0(1:8), B1(1:8),C2(1:9), B3(1:8) for the rate-32/33 code by multiplexing coded anduncoded bits. The 32-bit input is separated by a demultiplexer 400 intotwo sets of two 8-bit symbols B0(1:8), B2(1:8) and B1(1:8), B3(1:8). 16bits in one of the sets, B0(1:8) and B2(1:8) for example, are encoded bythe rate-16/17 mother code encoder 402 which outputs 17 encoded bitsC0(1:8), C2(1:9). The 16 bits in the other set, B1(1:8), B3(1:8), remainunencoded. A multiplexer 404 multiplexes the four 8-bit symbols into a33-bit codeword C0(1:8), B1(1:8), C2(1:9), B3(1:8). Although notillustrated in the Figures, a 48-bit input is transformed into a 49-bitcodeword by a comparable process.

The rate-32/33 PRML(G=14, I=11, M=23) code rules out both DSS and ReSync and has an error propagation of 8 NRZ bits assuming 4-way C1interleaving. FIG. 5A illustrates a 4-way interleaving (multiplexing)mechanism of 8-bit symbols at the output of four C1 Reed-Solomonencoders which may be implemented for the rate-32/33 PRML(G=14, I=11,M=23) code of the present invention. FIG. 5B is a block diagram of suchan interleaving scheme. Four C1 encoders 500A, 500B, 500C, 500D processseparate inputs and their outputs input into a multiplexer 502. Theleast and most significant bits of a sequence of bits 502 is also inputinto the multiplexer 502. The output of the multiplexer 502 B0, B1, B2,B3 provides a 32-bit input to a rate-32/33 RLL encoder 504. These fours=8-bit symbols are encoded by the encoder 504 (in the mannerillustrated in FIG. 4) and the 4-way interleaved 33-bit codeword, C0,B1, C2, B3, is output. Although not illustrated in the Figures, theblock diagram illustrating an interleaving mechanism for the rate-48/49code would include comparable functional blocks.

Rate-48/49 PRML(G=22, I=15, M=31) Code (RLL 2)

In an embodiment of a rate-48/49 PRML code, m=48, n=16, s=8, Q₁=2, P₁=4,P₂=2 and P₃=2. The rate-16/17 PRML(G=6, I=7, M=15) mother code may beused to obtain a rate-48/49 PRML(G=22, I=15, M=31) code by breaking thecodewords into P₃=2 pieces (8 bits and 9 bits) and inserting (m−n)/s=4uncoded bytes in between (a coded block of 8 bits or 9 bits is alwayspreceded and followed by two uncoded bytes). Coded data is precodedusing a 1/(1⊕D²) precoder and uncoded data may either be not precoded atall, 1/(1⊕D) precoded or 1/(1⊕D²) precoded. From an error-rateperformance viewpoint, it may be preferable to not use any precoding forthe uncoded data. However, because 1/(1⊕D) precoding is already used inconjunction with write equalization in LTO 1-4, it may be therefore moredesirable to use 1/(1⊕D) precoding. FIG. 6 illustrates a 4-way C1interleaving scheme which may be implemented for the rate-48/49PRML(G=22, I=15, M=31) code.

Rate-48/49 PRML(G=14, I=19, M=39) Code (RLL 3)

In another embodiment of a rate-48/49 PRML code, m=48, n=16, s=8, Q₁=2,P₁=4, P₂=2 and P₃=4. A rate-48/49 PRML(G=14, I=19, M=39) code may beobtained by breaking the codewords of the rate-16/17 PRML(G=6, I=7,M=15) code into P₃=4 coded blocks (4 bits+4 bits+5 bits+4 bits) andinserting (m−n)/s=4 uncoded bytes in between (a coded block of 4 bits or5 bits is always preceded and followed by an uncoded byte). However,this code may require redefining DSS and Re Sync patterns to ensure thatthe maximum length of modulation-encoded data that looks like DSS or ReSync is not prohibitively large. FIG. 7 illustrates a 4-way C1interleaving scheme which may be implemented for the rate-48/49PRML(G=14, I=19, M=39) code.

It is important to note that while the present invention has beendescribed in the context of a fully functioning data processing system,those of ordinary skill in the art will appreciate that the processes ofthe present invention are capable of being distributed in the form of acomputer readable medium of instructions and a variety of forms and thatthe present invention applies regardless of the particular type ofsignal bearing media actually used to carry out the distribution.Examples of computer readable media include recordable-type media suchas a floppy disk, a hard disk drive, a RAM, and CD-ROMs andtransmission-type media.

The description of the present invention has been presented for purposesof illustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the art. Theembodiment was chosen and described in order to best explain theprinciples of the invention, the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated. Moreover, although described above withrespect to methods and systems, the need in the art may also be met witha computer program product containing instructions for encoding a datainput sequence of m bits into an output sequence codeword of m+1 bits ora method for deploying computing infrastructure comprising integratingcomputer readable code into a computing system for encoding a data inputsequence of m bits into an output sequence codeword of m+1 bits.

1. (canceled)
 2. A method for encoding a data input sequence of m bitsinto an output sequence codeword of m+1 bits, where m is an integermultiple of 16, the method comprising the steps of: receiving anunencoded m-bit input sequence; separating the m-bit input sequence intoa first unencoded set of 16 bits and a second unencoded set of m−16bits; encoding the first unencoded set into a rate-16/17 PRML (G=6, I=7,M=15) encoded sequence; and multiplexing the 16/17 encoded sequence withthe second unencoded set to generate an encoded sequence of arate-(m)/(m+1) PRML code.
 3. The method of claim 2, wherein m isselected from the group comprising 32 and
 48. 4. The method of claim 2,wherein the rate-(m)/(m+1) PRML code is selected from the groupcomprising a rate-32/33 PRML(G=14, I=11, M=23) code, a rate-48/49PRML(G=22, I=15, M=31) code and a rate-48/49 PRML(G=14, I=19, M=39)code.
 5. The method of claim 2, wherein encoding the first unencoded setinto a rate-16/17 PRML (G=6, I=7, M=15) encoded sequence comprisesprocessing the first unencoded set through a plurality K encodingstages, each having an output o_(k) ^(E)=M_(k) ^(E)n_(k) ^(E)=g_(k)^(E)(i_(k) ^(E))h_(k) ^(E)(i_(k) ^(E)), where the superscript E refersto the encoding operation, and the outputs of the first through K^(th)−1stages become the inputs to the second through K^(th) stages,respectively.
 6. The method of claim 5, wherein K=3 and: the output of afirst encoding stage comprises a PRML(G=6, I=9, M=20) code; the outputof a second encoding stage comprises a PRML(G=6, I=7, M=15) code; andthe output of a third encoding stage comprises a PRML(G=6, I=7, M=15)code.
 7. The method of claim 5, wherein K=3 and: for a first encodingstage: the input column vector is represented by: i₁ ^(E)=a^(T)=[a₁ a₂ .. . a₁₆]^(T); the transformation matrix is represented by:M₁^(E) = g₁^(E)(i₁^(E)) = [M_(1, 1)^(E)M_(1, 2)^(E)]$M_{1,1}^{E} = \begin{bmatrix}a_{9} & a_{1} & a_{1} & a_{1} & a_{1} & a_{1} & a_{9} & a_{1} & a_{5} & a_{5} & a_{5} & a_{5} & a_{1} & a_{1} & a_{1} & a_{1} \\a_{10} & a_{2} & a_{2} & a_{2} & a_{2} & a_{2} & a_{10} & a_{2} & a_{6} & a_{6} & a_{6} & a_{6} & a_{2} & a_{2} & a_{2} & a_{2} \\a_{11} & a_{3} & a_{3} & a_{3} & a_{3} & a_{3} & a_{11} & a_{3} & a_{7} & a_{7} & a_{7} & a_{7} & a_{3} & a_{3} & a_{3} & a_{3} \\a_{12} & a_{4} & a_{4} & a_{4} & a_{4} & a_{4} & a_{12} & a_{4} & a_{8} & a_{8} & a_{8} & a_{8} & a_{4} & a_{4} & a_{4} & a_{4} \\a_{5} & a_{9} & a_{5} & a_{5} & a_{5} & a_{5} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 \\a_{6} & a_{10} & a_{6} & a_{6} & a_{6} & a_{6} & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 \\a_{7} & a_{11} & a_{7} & a_{7} & a_{7} & a_{7} & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 1 \\a_{8} & a_{12} & a_{8} & a_{8} & a_{8} & a_{8} & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 \\0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\0 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\1 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\a_{13} & a_{13} & a_{13} & a_{13} & a_{13} & a_{9} & a_{13} & a_{9} & a_{9} & a_{13} & a_{13} & a_{13} & a_{13} & a_{13} & a_{13} & a_{5} \\a_{14} & a_{14} & a_{14} & a_{14} & a_{14} & a_{10} & a_{14} & a_{10} & a_{10} & a_{14} & a_{14} & a_{14} & a_{14} & a_{14} & a_{14} & a_{6} \\a_{15} & a_{15} & a_{15} & a_{15} & a_{15} & a_{11} & a_{15} & a_{11} & a_{11} & a_{15} & a_{15} & a_{15} & a_{15} & a_{15} & a_{15} & a_{7} \\a_{16} & a_{16} & a_{16} & a_{16} & a_{16} & a_{12} & a_{16} & a_{12} & a_{12} & a_{16} & a_{16} & a_{16} & a_{16} & a_{16} & a_{16} & a_{8}\end{bmatrix}$ $M_{1,2}^{E} = \begin{bmatrix}a_{1} & a_{1} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & a_{1} \\a_{2} & a_{2} & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 1 & a_{2} \\a_{3} & a_{3} & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & a_{3} \\a_{4} & a_{4} & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & a_{4} \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{5} \\0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{6} \\1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & a_{7} \\1 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{8} \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{9} \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{10} \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{11} \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & a_{12} \\a_{5} & a_{5} & a_{9} & a_{13} & a_{13} & a_{13} & a_{5} & a_{5} & a_{5} & a_{1} & a_{1} & a_{1} & 0 & 0 & 0 & a_{13} \\a_{6} & a_{6} & a_{10} & a_{14} & a_{14} & a_{14} & a_{6} & a_{6} & a_{6} & a_{2} & a_{2} & a_{2} & 0 & 0 & 0 & a_{14} \\a_{7} & a_{7} & a_{11} & a_{15} & a_{15} & a_{7} & a_{7} & a_{7} & a_{7} & a_{3} & a_{3} & a_{3} & 1 & 1 & 1 & a_{15} \\a_{8} & a_{8} & a_{12} & a_{16} & a_{16} & a_{16} & a_{8} & a_{8} & a_{8} & a_{4} & a_{4} & a_{4} & 1 & 1 & 1 & a_{16}\end{bmatrix}$ the partitioning column vector is represented by: n₁^(E)=h₁ ^(E)(i₁ ^(E))=P^(T)=[P₁ P₂ . . . P₃₂]^(T), where the followingsix auxiliary variables:v ₁= a ₁ +a ₂ +a ₃ +a ₄v ₂= a ₅ +a ₆ +a ₇ +a ₈v ₃= a ₉ +a ₁₀ +a ₁₁ +a ₁₂v₄=ā₉a₁₀ā₁₁ā₁₂v₅=a₉a₁₀a₁₁a₁₂v ₆= a ₁₃ +a ₁₄ +a ₁₅ +a ₁₆ are used to express the components of thepartitioning vector: p₁ = v₁ v ₂ v ₃ v ₄ v ₅ v ₆, p₂ = v ₁v₂ v ₃ v ₄ v ₅v ₆, p₃ = v ₁ v ₂v₃ v ₄ v ₅ v ₆, p₄ = v ₁ v ₂ v ₃v₄ v ₅ v ₆, p₅ = v ₁ v₂ v ₃ v ₄v₅ v ₆, p₆ = v ₁ v ₂ v ₃ v ₄ v ₅v₆, p₇ = v₁v₂ v ₃ v ₄ v ₅ v ₆,p₈ = v ₁v₂ v ₃ v ₄ v ₅v₆, p₉ = v₁ v ₂ v ₃ v ₄ v ₅v₆, p₁₀ = v₁ v ₂v₃ v ₄v ₅ v ₆, p₁₁ = v₁ v ₂ v ₃v₄ v ₅ v ₆, p₁₂ = v₁ v ₂ v ₃ v ₄v₅ v ₆, p₁₃ = v₁v₂v₃ v ₄ v ₅ v ₆, p₁₄ = v ₁v₂ v ₃v₄ v ₅ v ₆, p₁₅ = v ₁v₂ v ₃ v ₄v₅ v ₆,p₁₆ = v ₁ v ₂v₃ v ₄ v ₅v₆, p₁₇ = v ₁ v ₂ v ₃v₄ v ₅v₆, p₁₈ = v ₁ v ₂ v ₃v ₄v₅v₆, p₁₉ = v₁v₂ v ₃ v ₄ v ₅v₆, p₂₀ = v₁v₂v₃ v ₄ v ₅ v ₆, p₂₁ = v₁v₂v ₃v₄ v ₅ v ₆, p₂₂ = v₁v₂ v ₃ v ₄v₅ v ₆, p₂₃ = v₁ v ₂v₃ v ₄ v ₅v₆, p₂₄ =v₁ v ₂ v ₃v₄ v ₅v₆, p₂₅ = v₁ v ₂ v ₃ v ₄v₅v₆, p₂₆ = v ₁v₂v₃ v ₄ v ₅v₆,p₂₇ = v ₁v₂ v ₃v₄ v ₅v₆, p₂₈ = v ₁v₂ v ₃ v ₄v₅v₆, p₂₉ = v₁v₂v₃ v ₄ v₅v₆, p₃₀ = v₁v₂ v ₃v₄ v ₅v₆, p₃₁ = v₁v₂ v ₃ v ₄v₅v₆, p₃₂ = v ₁ v ₂ v ₃ v₄ v ₅ v ₆,

and the output vector is represented by: o₁ ^(E)=M₁ ^(E)n₁^(E)=b^(T)=[b₁ b₂ . . . b₁₇]^(T); for a second encoding stage: the inputcolumn vector is represented by: i₂ ^(E)=b^(T)=[b₁ b₂ . . . b₁₇]^(T);the transformation matrix is represented by: M₂ ^(E)=g₂ ^(E)(i₂ ^(E))$M_{2}^{E} = \begin{bmatrix}b_{2} & 0 & b_{4} & b_{14} & b_{6} & b_{10} & b_{8} & b_{12} & b_{9} & 0 & b_{11} & 0 & b_{13} & 1 & b_{15} & b_{16} & b_{17} \\b_{14} & 1 & b_{2} & b_{2} & b_{11} & b_{10} & b_{13} & b_{12} & b_{1} & 0 & b_{3} & 0 & b_{5} & 1 & b_{7} & b_{16} & b_{17} \\b_{14} & b_{15} & 1 & b_{2} & b_{10} & b_{11} & b_{12} & b_{13} & 1 & 1 & 1 & 1 & 1 & 0 & 1 & b_{16} & b_{17} \\b_{1} & b_{2} & b_{2} & b_{2} & b_{5} & b_{6} & b_{7} & b_{8} & b_{9} & b_{10} & b_{11} & b_{12} & b_{13} & b_{14} & b_{15} & b_{16} & b_{17}\end{bmatrix}^{T}$ the partitioning column vector is represented by: n₂^(E)=h₂ ^(E)(i₂ ^(E))=q^(T)=[q₁ q₂ q₃ q₄]^(T) where:q ₁= b ₁ +b ₃ +b ₅ +b ₇q ₂= b ₂ +b ₄ +b ₆ +b ₈q₃=b₁b₂b₃b₄b₅b₆b₇b₈q ₄= q ₁ +q ₂ +q ₃ and the output column vector is represented by: o₂^(E)=M₂ ^(E)n₂ ^(E)=c^(T)=[c₁ c₂ . . . c₁₇]^(T); and for a thirdencoding stage: the input column vector is represented by: i₃^(E)=c^(T)=[c₁ c₂ . . . c₁₇]^(T); the transformation matrix isrepresented by: M₃ ^(E)=g₃ ^(E)(i₃ ^(E)) $M_{3}^{E} = \begin{bmatrix}c_{10} & c_{12} & 1 & 1 & 0 & 0 & 0 & 0 & c_{9} & 1 & c_{11} & 0 & c_{13} & c_{14} & c_{15} & c_{16} & c_{17} \\c_{1} & c_{2} & c_{3} & c_{4} & c_{5} & c_{6} & 1 & 1 & 0 & c_{7} & 0 & c_{8} & 0 & 1 & 1 & 0 & 1 \\c_{1} & c_{2} & c_{3} & c_{4} & c_{5} & c_{6} & c_{7} & c_{8} & c_{9} & c_{10} & c_{11} & c_{12} & c_{13} & c_{14} & c_{15} & c_{16} & c_{17}\end{bmatrix}^{T}$ the partitioning column vector is represented by: n₃^(E)=h₃ ^(E)(i₃ ^(E))=u^(T)=[u₁ u₂ u₃]^(T) whereu₁= c ₁ c ₂ c ₃c₄c₅ c ₆ c ₇ c ₈u₂=c₉c₁₀c₁₁c₁₂c₁₃c₁₄c₁₅c₁₆c₁₇u ₃= u ₁ +u ₂ and the output column vector is represented by: o₃ ^(E)=M₃^(E)n₃ ^(E)=y^(T)=[y₁ y₂ . . . y₁₇]^(T).
 8. The method of claim 7,further comprising: receiving an encoded input sequence of arate-(m)/(m+1) PRML code; separating the received encoded input sequenceinto a first received encoded rate-16/17 PRML (G=6, I=7, M=15) sequenceand a second received sequence of m−16 bits; decoding the first receivedencoded rate-16/17 sequence into a 16-bit decoded sequence in K=3decoding stages by performing operations in the 1^(st) decoding stagewhich are inverse to the operations performed by the 3^(rd) encodingstage, performing operations in the 2^(nd) decoding stage which areinverse to the operations performed by the 2^(nd) encoding stage andperforming operations in the 3^(rd) decoding stage which are inverse tothe operations performed by the 1^(st) encoding stage; and multiplexingthe 16-bit decoded sequence with the second received sequence of m−16bits to generate the decoded m-bit sequence which is equal to theoriginal unencoded m-bit sequence if the received bits are not in error.9. The method of claim 2, wherein: the second unencoded sequencecomprises 16 bits; the rate-(m)/(m+1) PRML code comprises a rate-32/33PRML(G=14, I=11, M=23) code; and the method further comprises: dividingthe 16/17 encoded sequence into two encoded subblocks of 8 and 9 bits,respectively; dividing the second unencoded set into two unencodedsubblocks of 8 bits each; and multiplexing the 16/17 encoded sequencewith the second unencoded set by interleaving the two unencodedsubblocks with the two encoded subblocks.
 10. The method of claim 2,wherein: the rate-(m)/(m+1) PRML code comprises a rate-48/49 PRML(G=22,I=15, M=31) code; the second unencoded sequence comprises 32 bits; andthe method further comprises: dividing the 16/17 encoded sequence intotwo encoded subblocks of 8 and 9 bits, respectively; dividing the secondunencoded set into two unencoded subblocks of 16 bits each; andmultiplexing the 16/17 encoded sequence with the second unencoded set byinterleaving the two unencoded subblocks with the two encoded subblocks.11. The method of claim 2, wherein: the second unencoded sequencecomprises 32 bits; the rate-(m)/(m+1) PRML code comprises a rate-48/49PRML(G=14, I=19, M=39) code; and the method further comprises: dividingthe 16/17 encoded sequence into four encoded subblocks of 4, 4, 5 and 4bits, respectively; dividing the second unencoded set into fourunencoded subblocks of 8 bits each; and multiplexing the 16/17 encodedsequence with the second unencoded set by interleaving the fourunencoded subblocks with the four encoded subblocks.
 12. The method ofclaim 2, further comprising: receiving an encoded input sequence of arate-(m)/(m+1) PRML code; separating the received encoded input sequenceinto a first received encoded rate-16/17 PRML (G=6, I=7, M=15) sequenceand a second received sequence of m−16 bits; decoding the first receivedencoded sequence into a 16-bit decoded sequence; and multiplexing the16-bit decoded sequence with the second received sequence to generatethe decoded m-bit sequence which is equal to the original unencodedm-bit sequence if the received bits are not in error.
 13. The method ofclaim 12, wherein decoding the first received encoded sequence into the16-bit decoded sequence comprises processing the first received encodedsequence through a plurality K decoding stages, each having an outputo_(k) ^(D)=M_(k) ^(D)n_(k) ^(D)=g_(k) ^(D)(i_(k) ^(D))h_(k) ^(D)(i_(k)^(D)), where the superscript D refers to the decoding operation, and theoutputs of the first through K^(th)−1 stages become the inputs to thesecond through K^(th) stages, respectively.
 14. A system for encoding adata input sequence of m bits into an output sequence codeword of m+1bits, where m is an integer multiple of 16, comprising: a demultiplexoroperable to receive an unencoded m-bit input sequence and separate them-bit input sequence into a first unencoded set of 16 bits and a secondunencoded set of m−16 bits; a plurality K of encoding stages operable toencode the first unencoded set into a rate-16/17 PRML (G=6, I=7, M=15)encoded sequence; and a multiplexor operable to multiplex the 16/17encoded sequence with the second unencoded set to generate an encodedsequence of a rate-(m)/(m+1) PRML code.
 15. The system of claim 14,wherein m is selected from the group comprising 32 and
 48. 16. Thesystem of claim 14, wherein the rate-(m)/(m+1) PRML code is selectedfrom the group comprising a rate-32/33 PRML(G=14, I=11, M=23) code, arate-48/49 PRML(G=22, I=15, M=31) code and a rate-48/49 PRML(G=14, I=19,M=39) code.
 17. The system of claim 14, wherein each encoding stage hasan output o_(k) ^(E)=M_(k) ^(E)n_(k) ^(E)=g_(k) ^(E)(i_(k) ^(E))h_(k)^(E)(i_(k) ^(E)), where the superscript E refers to the encodingoperation, and the outputs of the first through K^(th)−1 stages becomethe inputs to the second through K^(th) stages, respectively
 18. Thesystem of claim 17, further comprising: a demultiplexor operable toreceive an encoded input sequence of a rate-(m)/(m+1) PRML code andseparate the received encoded input sequence into a first receivedencoded rate-16/17 PRML (G=6, 1=7, M=15) sequence and a second receivedsequence of m−16 bits; K=3 decoding stages to decode the first receivedencoded rate-16/17 sequence into a 16-bit decoded sequence by performingoperations in the 1^(st) decoding stage which are inverse to theoperations performed by the 3^(rd) encoding stage, performing operationsin the 2^(nd) decoding stage which are inverse to the operationsperformed by the 2^(nd) encoding stage and performing operations in the3^(rd) decoding stage which are inverse to the operations performed bythe 1^(st) encoding stage; and a multiplexor operable to multiplex the16-bit decoded sequence with the second received sequence of m −16 bitsto generate the decoded m-bit sequence which is equal to the originalunencoded m-bit sequence if the received bits are not in error.
 19. Thesystem of claim 17 wherein K=3 and: a first encoding stage outputs aPRML(G=6, I=9, M=20) code; a second encoding stage outputs a PRML(G=6,I=7, M=15) code; and a third encoding stage outputs a PRML(G=6, I=7,M=15) code.
 20. The system of claim 14, wherein: the second unencodedsequence comprises 16 bits; the rate-(m)/(m+1) PRML code comprises arate-32/33 PRML(G=14, I=11, M=23) code; the demultiplexor is furtheroperable to divide the 16/17 encoded sequence into two encoded subblocksof 8 and 9 bits, respectively, and to divide the second unencoded setinto two unencoded subblocks of 8 bits each; and the multiplexor isfurther operable to multiplex the 16/17 encoded sequence with the secondunencoded set by interleaving the two unencoded subblocks with the twoencoded subblocks.
 21. The system of claim 14, wherein: the secondunencoded sequence comprises 32 bits; the rate-(m)/(m+1) PRML codecomprises a rate-48/49 PRML(G=22, I=15, M=31) code; the demultiplexor isfurther operable to divide the 16/17 encoded sequence into two encodedsubblocks of 8 and 9 bits, respectively, and to divide the secondunencoded set into two unencoded subblocks of 16 bits each; and themultiplexor is further operable to multiplex the 16/17 encoded sequencewith the second unencoded set by interleaving the two unencodedsubblocks with the two encoded subblocks.
 22. The system of claim 14,wherein: the second unencoded sequence comprises 32 bits; therate-(m)/(m+1) PRML code comprises a rate-48/49 PRML(G=14, I=19, M=39)code; the demultiplexor is further operable to divide the 16/17 encodedsequence into four encoded subblocks of 4, 4, 5 and 4 bits,respectively, and to divide the second unencoded set into four unencodedsubblocks of 8 bits each; and the multiplexor is further operable tomultiplex the 16/17 encoded sequence with the second unencoded set byinterleaving the four unencoded subblocks with the four encodedsubblocks.
 23. The system of claim 14, further comprising: ademultiplexor operable for receiving an encoded input sequence of arate-(m)/(m+1) PRML code and separating the received encoded inputsequence into a first received encoded rate-16/17 PRML (G=6, I=7, M=15)sequence and a second received sequence of m−16 bits; a decoder operableto decode the first received encoded sequence into a 16-bit decodedsequence; and a multiplexor operable to multiplex the 16-bit decodedsequence with the second received sequence to generate the decoded m-bitsequence which is equal to the original unencoded m-bit sequence if thereceived bits are not in error.
 24. The system of claim 23, wherein thedecoder is operable to decode the first received encoded sequence intothe 16-bit decoded sequence comprises processing the first receivedencoded sequence through a plurality K decoding stages, each having anoutput o_(k) ^(D)=M_(k) ^(D)n_(k) ^(D)=g_(k) ^(D)(i_(k) ^(D))h_(k)^(D)(i_(k) ^(D)), where the superscript D refers to the decodingoperation, and the outputs of the first through K^(th)−1 stages becomethe inputs to the second through K^(th) stages, respectively.
 25. Anencoder for encoding a data input sequence of m bits into an outputsequence codeword of m+1 bits, where m is an integer multiple of an ECCsymbol size s, comprising: a demultiplexor operable to receive a datastream of unencoded m-bit input sequences and divide each m-bit inputsequence into a first block of n bits and a second block of m−nunencoded bits, where n is an integer multiple of s; a plurality ofencoder stages operable to: encode the first block of n bits into afirst set of n+1 encoded bits, wherein at least one of P1 subblocks ofthe first set of n+1 bits satisfies a G constraint, an M constraint andan/constraint; map in a one-to-one manner the first set of n+1 encodedbits into a second set of n+1 encoded bits wherein, at least one of P2subblocks of the second set of n+1 bits gives rise to at least Q1transitions after 1/(1+D²) precoding; and divide the second set of n+1encoded bits into P3 encoded subblocks; and a multiplexor operable tointerleave the P3 encoded subblocks among (m-n)/s unencoded symbols soas to form the (m+1)-bit output sequence codeword to be stored on a datastorage medium.
 26. The encoder of claim 25, wherein the P3 encodedsubblocks form a rate-(m)/(m+1) PRML code selected from the groupcomprising a rate-32/33 PRML(G=14, I=11, M=23) code, a rate-48/49PRML(G=22, I=15, M=31) code and a rate-48/49 PRML(G=14, I=19, M=39)code.
 27. The encoder of claim 25, wherein each encoding stage has anoutput o_(k) ^(E)=M_(k) ^(E)n_(k) ^(E)=g_(k) ^(E)(i_(k) ^(E))h_(k)^(E)(i_(k) ^(E)), where the superscript E refers to the encodingoperation, and the outputs of the first through K^(th)−1 stages becomethe inputs to the second through K^(th) stages, respectively
 28. Theencoder of claim 27 wherein K=3 and: a first encoding stage outputs aPRML(G=6, I=9, M=20) code; a second encoding stage outputs a PRML(G=6,I=7, M=15) code; and a third encoding stage outputs a PRML(G=6, I=7,M=15) code.
 29. The encoder of claim 25, comprising a decoder fordecoding a received sequence of m+1 bits into an output sequence of mbits, where m is an integer multiple of an ECC symbol size s,comprising: a demultiplexor operable to receive a data stream of areceived encoded rate-(m)/(m+1) codeword sequence and divide thereceived codeword sequence into a first received encoded rate-(n)/(n+1)sequence and a second block of m−n received bits, where n is an integermultiple of s; a plurality of decoder stages operable to decode thereceived rate-(n)/(n+1) encoded sequence into n decoded bits; and amultiplexor operable to interleave the n decoded bits with a secondblock of m−n received bits so as to form an m-bit sequence which isequal to the original unencoded m-bit sequence if the received bits arenot in error.
 30. The decoder of claim 29, wherein decoding therate-(n)/(n+1) sequence into n decoded bits comprises processing therate-(n)/(n+1) sequence through a plurality K decoding stages, eachhaving an output o_(k) ^(D)=M_(k) ^(D)n_(k) ^(D)=g_(k) ^(D)=g_(k)^(D)(i_(k) ^(D))h_(k) ^(D)(i_(k) ^(D)), where the superscript D refersto the decoding operation, and the outputs of the first through K^(th)−1stages become the inputs to the second through K^(th) stages,respectively.